Re: [PATCH] q35：Enable TSEG only when G_SMRAME and TSEG_EN both enabled

[Paolo Bonzini]

On 6/15/22 05:45, Zhenzhong Duan wrote:
> According to spec:
> "TSEG Enable (T_EN): Enabling of SMRAM memory for Extended SMRAM space
> only. When G_SMRAME = 1 and TSEG_EN = 1, the TSEG is enabled to appear
> in the appropriate physical address space. Note that once D_LCK is set,
> this bit becomes read only."
>
> Changed to match the spec description.
>
> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
> ---
>   hw/pci-host/q35.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
> index ab5a47aff560..20da1213747c 100644
> --- a/hw/pci-host/q35.c
> +++ b/hw/pci-host/q35.c
> @@ -379,7 +379,8 @@ static void mch_update_smram(MCHPCIState *mch)
>           memory_region_set_enabled(&mch->high_smram, false);
>       }
>   
> -    if (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_T_EN) {
> +    if ((pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_T_EN) &&
> +        (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_G_SMRAME)) {
>           switch (pd->config[MCH_HOST_BRIDGE_ESMRAMC] &
>                   MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK) {
>           case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB:

Queued, thanks.

paolo