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[PATCH 8/9] target/riscv: debug: Return 0 if previous value written to t
From: |
frank . chang |
Subject: |
[PATCH 8/9] target/riscv: debug: Return 0 if previous value written to tselect >= number of triggers |
Date: |
Fri, 10 Jun 2022 13:13:25 +0800 |
From: Frank Chang <frank.chang@sifive.com>
If the value written to tselect is greater than or equal to the number
of supported triggers, then the following reads of tselect would return
value 0.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu.h | 1 +
target/riscv/debug.c | 6 ++++++
2 files changed, 7 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index bac5f00722..c7ee3f80e6 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -289,6 +289,7 @@ struct CPUArchState {
/* trigger module */
target_ulong trigger_cur;
+ target_ulong trigger_prev;
target_ulong tdata1[RV_MAX_TRIGGERS];
target_ulong tdata2[RV_MAX_TRIGGERS];
target_ulong tdata3[RV_MAX_TRIGGERS];
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index ce9ff15d75..83b72fa1b9 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -158,6 +158,10 @@ bool tdata_available(CPURISCVState *env, int tdata_index)
target_ulong tselect_csr_read(CPURISCVState *env)
{
+ if (env->trigger_prev >= RV_MAX_TRIGGERS) {
+ return 0;
+ }
+
return env->trigger_cur;
}
@@ -166,6 +170,8 @@ void tselect_csr_write(CPURISCVState *env, target_ulong val)
if (val < RV_MAX_TRIGGERS) {
env->trigger_cur = val;
}
+
+ env->trigger_prev = val;
}
static target_ulong tdata1_validate(CPURISCVState *env, target_ulong val,
--
2.36.1
- [PATCH 0/9] Improve RISC-V Debug support, frank . chang, 2022/06/10
- [PATCH 1/9] target/riscv: debug: Determine the trigger type from tdata1.type, frank . chang, 2022/06/10
- [PATCH 8/9] target/riscv: debug: Return 0 if previous value written to tselect >= number of triggers,
frank . chang <=
- [PATCH 2/9] target/riscv: debug: Introduce build_tdata1() to build tdata1 register content, frank . chang, 2022/06/10
- [PATCH 3/9] target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs, frank . chang, 2022/06/10
- [PATCH 4/9] target/riscv: debug: Restrict the range of tselect value can be written, frank . chang, 2022/06/10
- [PATCH 5/9] target/riscv: debug: Introduce tinfo CSR, frank . chang, 2022/06/10
- [PATCH 6/9] target/riscv: debug: Create common trigger actions function, frank . chang, 2022/06/10