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[PULL 23/25] target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable opt
From: |
Alistair Francis |
Subject: |
[PULL 23/25] target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail agnostic behavior |
Date: |
Fri, 10 Jun 2022 14:26:53 +1000 |
From: eopXD <eop.chen@sifive.com>
According to v-spec, tail agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of tail policies, QEMU should be able to simulate the tail
agnostic behavior as "set tail elements' bits to all 1s".
There are multiple possibility for agnostic elements according to
v-spec. The main intent of this patch-set tries to add option that
can distinguish between tail policies. Setting agnostic elements to
all 1s allows QEMU to express this.
This commit adds option 'rvv_ta_all_1s' is added to enable the
behavior, it is default as disabled.
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165449614532.19704.7000832880482980398-16@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0497af45cc..e5aa1e9c1b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -918,6 +918,8 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string,
false),
+
+ DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false),
DEFINE_PROP_END_OF_LIST(),
};
--
2.36.1
- [PULL 16/25] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions, (continued)
- [PULL 16/25] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions, Alistair Francis, 2022/06/10
- [PULL 14/25] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions, Alistair Francis, 2022/06/10
- [PULL 15/25] target/riscv: rvv: Add tail agnostic for vector integer shift instructions, Alistair Francis, 2022/06/10
- [PULL 18/25] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions, Alistair Francis, 2022/06/10
- [PULL 19/25] target/riscv: rvv: Add tail agnostic for vector floating-point instructions, Alistair Francis, 2022/06/10
- [PULL 20/25] target/riscv: rvv: Add tail agnostic for vector reduction instructions, Alistair Francis, 2022/06/10
- [PULL 21/25] target/riscv: rvv: Add tail agnostic for vector mask instructions, Alistair Francis, 2022/06/10
- [PULL 25/25] target/riscv: trans_rvv: Avoid assert for RV32 and e64, Alistair Francis, 2022/06/10
- [PULL 24/25] target/riscv: Don't expose the CPU properties on names CPUs, Alistair Francis, 2022/06/10
- [PULL 22/25] target/riscv: rvv: Add tail agnostic for vector permutation instructions, Alistair Francis, 2022/06/10
- [PULL 23/25] target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail agnostic behavior,
Alistair Francis <=
- Re: [PULL 00/25] riscv-to-apply queue, Richard Henderson, 2022/06/10