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[PULL 25/25] target/riscv: trans_rvv: Avoid assert for RV32 and e64
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From: |
Alistair Francis |
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Subject: |
[PULL 25/25] target/riscv: trans_rvv: Avoid assert for RV32 and e64 |
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Date: |
Fri, 10 Jun 2022 14:26:55 +1000 |
From: Alistair Francis <alistair.francis@wdc.com>
When running a 32-bit guest, with a e64 vmv.v.x and vl_eq_vlmax set to
true the `tcg_debug_assert(vece <= MO_32)` will be triggered inside
tcg_gen_gvec_dup_i32().
This patch checks that condition and instead uses tcg_gen_gvec_dup_i64()
is required.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1028
Suggested-by: Robert Bu <robert.bu@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220608234701.369536-1-alistair.francis@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 4f84d4878a..6c091824b6 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2128,8 +2128,16 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x
*a)
s1 = get_gpr(s, a->rs1, EXT_SIGN);
if (s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
- tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd),
- MAXSZ(s), MAXSZ(s), s1);
+ if (get_xl(s) == MXL_RV32 && s->sew == MO_64) {
+ TCGv_i64 s1_i64 = tcg_temp_new_i64();
+ tcg_gen_ext_tl_i64(s1_i64, s1);
+ tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
+ MAXSZ(s), MAXSZ(s), s1_i64);
+ tcg_temp_free_i64(s1_i64);
+ } else {
+ tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd),
+ MAXSZ(s), MAXSZ(s), s1);
+ }
} else {
TCGv_i32 desc;
TCGv_i64 s1_i64 = tcg_temp_new_i64();
--
2.36.1
- [PULL 12/25] target/riscv: rvv: Add tail agnostic for vv instructions, (continued)
- [PULL 12/25] target/riscv: rvv: Add tail agnostic for vv instructions, Alistair Francis, 2022/06/10
- [PULL 17/25] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions, Alistair Francis, 2022/06/10
- [PULL 10/25] target/riscv: rvv: Rename ambiguous esz, Alistair Francis, 2022/06/10
- [PULL 16/25] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions, Alistair Francis, 2022/06/10
- [PULL 14/25] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions, Alistair Francis, 2022/06/10
- [PULL 15/25] target/riscv: rvv: Add tail agnostic for vector integer shift instructions, Alistair Francis, 2022/06/10
- [PULL 18/25] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions, Alistair Francis, 2022/06/10
- [PULL 19/25] target/riscv: rvv: Add tail agnostic for vector floating-point instructions, Alistair Francis, 2022/06/10
- [PULL 20/25] target/riscv: rvv: Add tail agnostic for vector reduction instructions, Alistair Francis, 2022/06/10
- [PULL 21/25] target/riscv: rvv: Add tail agnostic for vector mask instructions, Alistair Francis, 2022/06/10
- [PULL 25/25] target/riscv: trans_rvv: Avoid assert for RV32 and e64,
Alistair Francis <=
- [PULL 24/25] target/riscv: Don't expose the CPU properties on names CPUs, Alistair Francis, 2022/06/10
- [PULL 22/25] target/riscv: rvv: Add tail agnostic for vector permutation instructions, Alistair Francis, 2022/06/10
- [PULL 23/25] target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail agnostic behavior, Alistair Francis, 2022/06/10
- Re: [PULL 00/25] riscv-to-apply queue, Richard Henderson, 2022/06/10