Re: [PATCH 1/2] target/arm: SCR_EL3 bits 4,5 are always res0

[Peter Maydell]

On Sun, 5 Jun 2022 at 17:14, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> These bits do not depend on whether or not el1 supports aa32.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Isn't this effectively reverting commit 10d0ef3e6cfe2, which
got applied as a bug fix last year ?

In particular, the reason we need to check something is that even
if the CPU is entirely AArch32-only, reset of the register is
handled by scr_reset() on the AArch64 reginfo struct, so on reset
we need to give the correct answer for the CPU and not assume
"regdef is AA64" implies "EL3 is AA64".

We should probably be checking "is EL3 AArch64 or AArch32" rather
than "does EL1 support AArch32", though...

There's a testcase in the original patch cover letter for the
bug it's trying to fix:
https://lore.kernel.org/qemu-devel/20210203165552.16306-1-michael.nawrocki@gtri.gatech.edu/

thanks
-- PMM