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[PULL 36/55] target/arm: Rename TBFLAG_A64 ZCR_LEN to VL
From: |
Peter Maydell |
Subject: |
[PULL 36/55] target/arm: Rename TBFLAG_A64 ZCR_LEN to VL |
Date: |
Thu, 9 Jun 2022 10:05:18 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
With SME, the vector length does not only come from ZCR_ELx.
Comment that this is either NVL or SVL, like the pseudocode.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220607203306.657998-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 3 ++-
target/arm/translate-a64.h | 2 +-
target/arm/translate.h | 2 +-
target/arm/helper.c | 2 +-
target/arm/translate-a64.c | 2 +-
target/arm/translate-sve.c | 2 +-
6 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 0ee1705a4fa..e791ffdd6b6 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3241,7 +3241,8 @@ FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not
cached. */
*/
FIELD(TBFLAG_A64, TBII, 0, 2)
FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2)
-FIELD(TBFLAG_A64, ZCR_LEN, 4, 4)
+/* The current vector length, either NVL or SVL. */
+FIELD(TBFLAG_A64, VL, 4, 4)
FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1)
FIELD(TBFLAG_A64, BT, 9, 1)
FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */
diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
index f2e8ee0ee1f..dbc917ee65b 100644
--- a/target/arm/translate-a64.h
+++ b/target/arm/translate-a64.h
@@ -104,7 +104,7 @@ static inline TCGv_ptr vec_full_reg_ptr(DisasContext *s,
int regno)
/* Return the byte size of the "whole" vector register, VL / 8. */
static inline int vec_full_reg_size(DisasContext *s)
{
- return s->sve_len;
+ return s->vl;
}
bool disas_sve(DisasContext *, uint32_t);
diff --git a/target/arm/translate.h b/target/arm/translate.h
index 9f0bb270c5b..f473a21ed48 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -42,7 +42,7 @@ typedef struct DisasContext {
bool ns; /* Use non-secure CPREG bank on access */
int fp_excp_el; /* FP exception EL or 0 if enabled */
int sve_excp_el; /* SVE exception EL or 0 if enabled */
- int sve_len; /* SVE vector length in bytes */
+ int vl; /* current vector length in bytes */
/* Flag indicating that exceptions from secure mode are routed to EL3. */
bool secure_routed_to_el3;
bool vfp_enabled; /* FP enabled via FPSCR.EN */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 37cf9fa6aba..c228deca755 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -11181,7 +11181,7 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState
*env, int el, int fp_el,
zcr_len = sve_zcr_len_for_el(env, el);
}
DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el);
- DP_TBFLAG_A64(flags, ZCR_LEN, zcr_len);
+ DP_TBFLAG_A64(flags, VL, zcr_len);
}
sctlr = regime_sctlr(env, stage1);
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 935e1929bb9..d438fb89e73 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -14608,7 +14608,7 @@ static void
aarch64_tr_init_disas_context(DisasContextBase *dcbase,
dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM);
dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL);
dc->sve_excp_el = EX_TBFLAG_A64(tb_flags, SVEEXC_EL);
- dc->sve_len = (EX_TBFLAG_A64(tb_flags, ZCR_LEN) + 1) * 16;
+ dc->vl = (EX_TBFLAG_A64(tb_flags, VL) + 1) * 16;
dc->pauth_active = EX_TBFLAG_A64(tb_flags, PAUTH_ACTIVE);
dc->bt = EX_TBFLAG_A64(tb_flags, BT);
dc->btype = EX_TBFLAG_A64(tb_flags, BTYPE);
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 836511d7191..67761bf2cc5 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -111,7 +111,7 @@ static inline int pred_full_reg_offset(DisasContext *s, int
regno)
/* Return the byte size of the whole predicate register, VL / 64. */
static inline int pred_full_reg_size(DisasContext *s)
{
- return s->sve_len >> 3;
+ return s->vl >> 3;
}
/* Round up the size of a register to a size allowed by
--
2.25.1
- [PULL 24/55] target/arm: Move {arm_s1_, }regime_using_lpae_format to tlb_helper.c, (continued)
- [PULL 24/55] target/arm: Move {arm_s1_, }regime_using_lpae_format to tlb_helper.c, Peter Maydell, 2022/06/09
- [PULL 34/55] target/arm: Move stage_1_mmu_idx, arm_stage1_mmu_idx to ptw.c, Peter Maydell, 2022/06/09
- [PULL 38/55] target/arm: Remove route_to_el2 check from sve_exception_el, Peter Maydell, 2022/06/09
- [PULL 41/55] target/arm: Use el_is_in_host for sve_zcr_len_for_el, Peter Maydell, 2022/06/09
- [PULL 04/55] xlnx_dp: fix the wrong register size, Peter Maydell, 2022/06/09
- [PULL 15/55] target/arm: Move get_phys_addr_pmsav8 to ptw.c, Peter Maydell, 2022/06/09
- [PULL 19/55] target/arm: Move m_is_{ppb,system}_region to ptw.c, Peter Maydell, 2022/06/09
- [PULL 21/55] target/arm: Move combine_cacheattrs and subroutines to ptw.c, Peter Maydell, 2022/06/09
- [PULL 27/55] target/arm: Move check_s2_mmu_setup to ptw.c, Peter Maydell, 2022/06/09
- [PULL 28/55] target/arm: Move aa32_va_parameters to ptw.c, Peter Maydell, 2022/06/09
- [PULL 36/55] target/arm: Rename TBFLAG_A64 ZCR_LEN to VL,
Peter Maydell <=
- [PULL 01/55] target/arm: Declare support for FEAT_RASv1p1, Peter Maydell, 2022/06/09
- [PULL 10/55] target/arm: Move get_phys_addr_v5 to ptw.c, Peter Maydell, 2022/06/09
- [PULL 17/55] target/arm: Move pmsav7_use_background_region to ptw.c, Peter Maydell, 2022/06/09
- [PULL 30/55] target/arm: Move regime_is_user to ptw.c, Peter Maydell, 2022/06/09
- [PULL 35/55] target/arm: Pass CPUARMState to arm_ld[lq]_ptw, Peter Maydell, 2022/06/09
- [PULL 33/55] target/arm: Move arm_cpu_get_phys_page_attrs_debug to ptw.c, Peter Maydell, 2022/06/09
- [PULL 26/55] target/arm: Move get_S1prot, get_S2prot to ptw.c, Peter Maydell, 2022/06/09
- [PULL 43/55] target/arm: Hoist arm_is_el2_enabled check in sve_exception_el, Peter Maydell, 2022/06/09
- [PULL 42/55] target/arm: Use el_is_in_host for sve_exception_el, Peter Maydell, 2022/06/09
- [PULL 44/55] target/arm: Do not use aarch64_sve_zcr_get_valid_len in reset, Peter Maydell, 2022/06/09