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Re: [RFC PATCH v2] RISC-V: Add Zawrs ISA extension support


From: Christoph Müllner
Subject: Re: [RFC PATCH v2] RISC-V: Add Zawrs ISA extension support
Date: Thu, 2 Jun 2022 17:51:53 +0200

On Thu, Jun 2, 2022 at 5:07 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 6/2/22 06:40, Christoph Muellner wrote:
> > diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc 
> > b/target/riscv/insn_trans/trans_rvzawrs.c.inc
> > new file mode 100644
> > index 0000000000..38b71d0085
> > --- /dev/null
> > +++ b/target/riscv/insn_trans/trans_rvzawrs.c.inc
>
> Typo in the filename -- s/rvz/rz/.

This was actually intended as other files are named using the same pattern
(ext={a,b,d,f,h,i,k,m,v,zfh} -> trans_rv${ext}.c.inc).
I had the impression that Zawrs would fit into the pattern as well.
But if you prefer trans_rzawrs.c.inc I can change accordingly.

>
> > +#define REQUIRE_ZAWRS(ctx) do {         \
> > +    if (!ctx->cfg_ptr->ext_zawrs) {     \
> > +        return false;                   \
> > +    }                                   \
> > +} while (0)
> > +
> > +static bool trans_wrs(DisasContext *ctx, arg_sfence_vm *a)
> > +{
> > +    REQUIRE_ZAWRS(ctx);
>
> No point in the macro for what will only ever be a single user.

Ok, will change.

Thanks!

>
> Otherwise, the implementation looks correct.
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
>
> r~



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