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[PATCH v10 03/16] target/hexagon: make slot number an unsigned
From: |
Anton Johansson |
Subject: |
[PATCH v10 03/16] target/hexagon: make slot number an unsigned |
Date: |
Wed, 1 Jun 2022 19:00:00 +0200 |
From: Paolo Montesel <babush@rev.ng>
Signed-off-by: Alessandro Di Federico <ale@rev.ng>
Signed-off-by: Paolo Montesel <babush@rev.ng>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
---
target/hexagon/genptr.c | 24 +++++++++++++-----------
target/hexagon/macros.h | 2 +-
2 files changed, 14 insertions(+), 12 deletions(-)
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index cd6af4bceb..df126de55b 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -30,7 +30,8 @@
#include "gen_tcg.h"
#include "gen_tcg_hvx.h"
-static inline void gen_log_predicated_reg_write(int rnum, TCGv val, int slot)
+static inline void gen_log_predicated_reg_write(int rnum, TCGv val,
+ uint32_t slot)
{
TCGv zero = tcg_constant_tl(0);
TCGv slot_mask = tcg_temp_new();
@@ -62,7 +63,8 @@ static inline void gen_log_reg_write(int rnum, TCGv val)
}
}
-static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val, int slot)
+static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val,
+ uint32_t slot)
{
TCGv val32 = tcg_temp_new();
TCGv zero = tcg_constant_tl(0);
@@ -394,7 +396,7 @@ static inline void gen_store_conditional8(DisasContext *ctx,
tcg_gen_movi_tl(hex_llsc_addr, ~0);
}
-static inline void gen_store32(TCGv vaddr, TCGv src, int width, int slot)
+static inline void gen_store32(TCGv vaddr, TCGv src, int width, uint32_t slot)
{
tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
tcg_gen_movi_tl(hex_store_width[slot], width);
@@ -402,49 +404,49 @@ static inline void gen_store32(TCGv vaddr, TCGv src, int
width, int slot)
}
static inline void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src,
- DisasContext *ctx, int slot)
+ DisasContext *ctx, uint32_t slot)
{
gen_store32(vaddr, src, 1, slot);
ctx->store_width[slot] = 1;
}
static inline void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src,
- DisasContext *ctx, int slot)
+ DisasContext *ctx, uint32_t slot)
{
TCGv tmp = tcg_constant_tl(src);
gen_store1(cpu_env, vaddr, tmp, ctx, slot);
}
static inline void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src,
- DisasContext *ctx, int slot)
+ DisasContext *ctx, uint32_t slot)
{
gen_store32(vaddr, src, 2, slot);
ctx->store_width[slot] = 2;
}
static inline void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src,
- DisasContext *ctx, int slot)
+ DisasContext *ctx, uint32_t slot)
{
TCGv tmp = tcg_constant_tl(src);
gen_store2(cpu_env, vaddr, tmp, ctx, slot);
}
static inline void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src,
- DisasContext *ctx, int slot)
+ DisasContext *ctx, uint32_t slot)
{
gen_store32(vaddr, src, 4, slot);
ctx->store_width[slot] = 4;
}
static inline void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src,
- DisasContext *ctx, int slot)
+ DisasContext *ctx, uint32_t slot)
{
TCGv tmp = tcg_constant_tl(src);
gen_store4(cpu_env, vaddr, tmp, ctx, slot);
}
static inline void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src,
- DisasContext *ctx, int slot)
+ DisasContext *ctx, uint32_t slot)
{
tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
tcg_gen_movi_tl(hex_store_width[slot], 8);
@@ -453,7 +455,7 @@ static inline void gen_store8(TCGv_env cpu_env, TCGv vaddr,
TCGv_i64 src,
}
static inline void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src,
- DisasContext *ctx, int slot)
+ DisasContext *ctx, uint32_t slot)
{
TCGv_i64 tmp = tcg_constant_i64(src);
gen_store8(cpu_env, vaddr, tmp, ctx, slot);
diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
index a78e84faa4..5ea2d54ebe 100644
--- a/target/hexagon/macros.h
+++ b/target/hexagon/macros.h
@@ -185,7 +185,7 @@
#define LOAD_CANCEL(EA) do { CANCEL; } while (0)
#ifdef QEMU_GENERATE
-static inline void gen_pred_cancel(TCGv pred, int slot_num)
+static inline void gen_pred_cancel(TCGv pred, uint32_t slot_num)
{
TCGv slot_mask = tcg_temp_new();
TCGv tmp = tcg_temp_new();
--
2.36.1
- [PATCH v10 00/16] target/hexagon: introduce idef-parser, Anton Johansson, 2022/06/01
- [PATCH v10 01/16] target/hexagon: update MAINTAINERS for idef-parser, Anton Johansson, 2022/06/01
- [PATCH v10 03/16] target/hexagon: make slot number an unsigned,
Anton Johansson <=
- [PATCH v10 02/16] target/hexagon: import README for idef-parser, Anton Johansson, 2022/06/01
- [PATCH v10 04/16] target/hexagon: make helper functions non-static, Anton Johansson, 2022/06/01
- [PATCH v10 06/16] target/hexagon: expose next PC in DisasContext, Anton Johansson, 2022/06/01
- [PATCH v10 09/16] target/hexagon: fix renamed package templates, Anton Johansson, 2022/06/01
- [PATCH v10 13/16] target/hexagon: import lexer for idef-parser, Anton Johansson, 2022/06/01
- [PATCH v10 14/16] target/hexagon: import parser for idef-parser, Anton Johansson, 2022/06/01
- [PATCH v10 05/16] target/hexagon: introduce new helper functions, Anton Johansson, 2022/06/01
- [PATCH v10 11/16] target/hexagon: regenerate docker/cirrus files, Anton Johansson, 2022/06/01
- [PATCH v10 16/16] target/hexagon: import additional tests, Anton Johansson, 2022/06/01
- [PATCH v10 07/16] target/hexagon: prepare input for the idef-parser, Anton Johansson, 2022/06/01