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[PULL v2 30/31] hw/core: tcg-cpu-ops.h: Update comments of debug_check_w
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From: |
Alistair Francis |
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Subject: |
[PULL v2 30/31] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint() |
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Date: |
Fri, 22 Apr 2022 10:36:55 +1000 |
From: Bin Meng <bin.meng@windriver.com>
This is now used by RISC-V as well. Update the comments.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220421003324.1134983-7-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/core/tcg-cpu-ops.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index fbe6b76764..78c6c6635d 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -90,6 +90,7 @@ struct TCGCPUOps {
/**
* @debug_check_watchpoint: return true if the architectural
* watchpoint whose address has matched should really fire, used by ARM
+ * and RISC-V
*/
bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
--
2.35.1
- [PULL v2 19/31] target/riscv/pmp: fix NAPOT range computation overflow, (continued)
- [PULL v2 19/31] target/riscv/pmp: fix NAPOT range computation overflow, Alistair Francis, 2022/04/21
- [PULL v2 21/31] hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT, Alistair Francis, 2022/04/21
- [PULL v2 22/31] hw/intc: Support 32/64-bit mtimecmp and mtime accesses in RISC-V ACLINT, Alistair Francis, 2022/04/21
- [PULL v2 20/31] hw/riscv: virt: fix DT property mmu-type when CPU mmu option is disabled, Alistair Francis, 2022/04/21
- [PULL v2 24/31] hw/intc: riscv_aclint: Add reset function of ACLINT devices, Alistair Francis, 2022/04/21
- [PULL v2 25/31] target/riscv: debug: Implement debug related TCGCPUOps, Alistair Francis, 2022/04/21
- [PULL v2 23/31] hw/intc: Make RISC-V ACLINT mtime MMIO register writable, Alistair Francis, 2022/04/21
- [PULL v2 26/31] target/riscv: cpu: Add a config option for native debug, Alistair Francis, 2022/04/21
- [PULL v2 27/31] target/riscv: csr: Hook debug CSR read/write, Alistair Francis, 2022/04/21
- [PULL v2 28/31] target/riscv: machine: Add debug state description, Alistair Francis, 2022/04/21
- [PULL v2 30/31] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint(),
Alistair Francis <=
- [PULL v2 29/31] target/riscv: cpu: Enable native debug feature, Alistair Francis, 2022/04/21
- [PULL v2 31/31] hw/riscv: boot: Support 64bit fdt address., Alistair Francis, 2022/04/21
- Re: [PULL v2 00/31] riscv-to-apply queue, Richard Henderson, 2022/04/22