RE: [PATCH v2 4/4] hw/nios2: Machine with a Vectored Interrupt Controller

[Amir Gonnen]

Hi Peter,

> Is a VIC a configurable option on the real hardware (well, FPGA image, I 
> guess) that this board is modelling ?
> I couldn't find any docs on it with a quick google.

This specific example-board from Intel does not provide a VIC option, as far as 
I know.  
(https://fpgacloud.intel.com/devstore/platform/15.1.0/Standard/max10-10m50-development-kit-ghrd-with-nios-iiddr3qspi-flashethernetmsgdmauartadc-with-linux/)
Unfortunately, I couldn't find a publicly available nios2 board with a VIC. 
I've added "10m50-ghrd-vic" as an example to demonstrate how to wire VIC.

In practice, we use Intel tooling (Quartus Prime) to generate both the hardware 
(nios2 + vic + other devices) and the software BSP that works with it.
That is probably the regular workflow. Since nios2 is a "soft" cpu on an FPGA, 
each one generates their own custom "board" wired with the devices they need, 
memories etc.
In the future I may be able to share Neuroblade's QEMU nios2 board because it 
is quite generic - it consumes a device tree, parses it, and wires devices 
according to it, so it can automatically match the generated HW.

> Also, I wonder if we should have a vic machine option to the machine rather 
> than creating a whole new machine type?

Sure, if you think it makes more sense.
How do you suggest doing that? A class property for the nios2 machine class? Or 
is there some other standard way for adding a machine specific option?

Thanks,
Amir


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