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[PATCH 1/5] hw/riscv/riscv_hart: free the harts array when the object is
From: |
Damien Hedde |
Subject: |
[PATCH 1/5] hw/riscv/riscv_hart: free the harts array when the object is finalized |
Date: |
Fri, 18 Feb 2022 17:46:42 +0100 |
The array is dynamically allocated by realize() depending on the
number of harts.
This clean-up removes memory leaks which would happen in the
'init->finalize' life-cycle use-case (happening when user creation
is allowed).
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
---
hw/riscv/riscv_hart.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
index 613ea2aaa0..4aed6c2a59 100644
--- a/hw/riscv/riscv_hart.c
+++ b/hw/riscv/riscv_hart.c
@@ -66,6 +66,13 @@ static void riscv_harts_realize(DeviceState *dev, Error
**errp)
}
}
+static void riscv_harts_finalize(Object *obj)
+{
+ RISCVHartArrayState *s = RISCV_HART_ARRAY(obj);
+
+ g_free(s->harts);
+}
+
static void riscv_harts_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -79,6 +86,7 @@ static const TypeInfo riscv_harts_info = {
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(RISCVHartArrayState),
.class_init = riscv_harts_class_init,
+ .instance_finalize = riscv_harts_finalize,
};
static void riscv_harts_register_types(void)
--
2.35.1
[PATCH 2/5] target/riscv: add riscv_cpu_release_claimed_interrupts function, Damien Hedde, 2022/02/18
[PATCH 3/5] hw/intc/sifive_plic: report errors and free allocated memory, Damien Hedde, 2022/02/18
[PATCH 4/5] hw/intc/riscv_aclint: swi: report errors and free allocated memory, Damien Hedde, 2022/02/18
[PATCH 5/5] hw/intc/riscv_aclint: mtimer: report errors and free allocated memory, Damien Hedde, 2022/02/18