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[PULL 11/40] target/riscv: Fix vill field write in vtype
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From: |
Alistair Francis |
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Subject: |
[PULL 11/40] target/riscv: Fix vill field write in vtype |
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Date: |
Sat, 12 Feb 2022 10:00:02 +1000 |
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
The guest should be able to set the vill bit as part of vsetvl.
Currently we may set env->vill to 1 in the vsetvl helper, but there
is nowhere that we set it to 0, so once it transitions to 1 it's stuck
there until the system is reset.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220201064601.41143-1-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/vector_helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 020d2e841f..3bd4aac9c9 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -71,6 +71,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong
s1,
env->vl = vl;
env->vtype = s2;
env->vstart = 0;
+ env->vill = 0;
return vl;
}
--
2.34.1
- [PULL 01/40] include: hw: remove ibex_plic.h, (continued)
- [PULL 01/40] include: hw: remove ibex_plic.h, Alistair Francis, 2022/02/11
- [PULL 02/40] Allow setting up to 8 bytes with the generic loader, Alistair Francis, 2022/02/11
- [PULL 03/40] target/riscv: correct "code should not be reached" for x-rv128, Alistair Francis, 2022/02/11
- [PULL 04/40] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig', Alistair Francis, 2022/02/11
- [PULL 05/40] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr, Alistair Francis, 2022/02/11
- [PULL 07/40] target/riscv: access cfg structure through DisasContext, Alistair Francis, 2022/02/11
- [PULL 06/40] target/riscv: access configuration through cfg_ptr in DisasContext, Alistair Francis, 2022/02/11
- [PULL 08/40] target/riscv: iterate over a table of decoders, Alistair Francis, 2022/02/11
- [PULL 09/40] target/riscv: Add XVentanaCondOps custom extension, Alistair Francis, 2022/02/11
- [PULL 10/40] target/riscv: add a MAINTAINERS entry for XVentanaCondOps, Alistair Francis, 2022/02/11
- [PULL 11/40] target/riscv: Fix vill field write in vtype,
Alistair Francis <=
- [PULL 12/40] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode, Alistair Francis, 2022/02/11
- [PULL 13/40] target/riscv: Implement SGEIP bit in hip and hie CSRs, Alistair Francis, 2022/02/11
- [PULL 14/40] target/riscv: Implement hgeie and hgeip CSRs, Alistair Francis, 2022/02/11
- [PULL 15/40] target/riscv: Improve delivery of guest external interrupts, Alistair Francis, 2022/02/11
- [PULL 16/40] target/riscv: Allow setting CPU feature from machine/device emulation, Alistair Francis, 2022/02/11
- [PULL 17/40] target/riscv: Add AIA cpu feature, Alistair Francis, 2022/02/11
- [PULL 18/40] target/riscv: Add defines for AIA CSRs, Alistair Francis, 2022/02/11
- [PULL 19/40] target/riscv: Allow AIA device emulation to set ireg rmw callback, Alistair Francis, 2022/02/11
- [PULL 21/40] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32, Alistair Francis, 2022/02/11
- [PULL 20/40] target/riscv: Implement AIA local interrupt priorities, Alistair Francis, 2022/02/11