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[PATCH v6 06/23] target/riscv: Add AIA cpu feature
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From: |
Anup Patel |
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Subject: |
[PATCH v6 06/23] target/riscv: Add AIA cpu feature |
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Date: |
Thu, 30 Dec 2021 18:05:22 +0530 |
From: Anup Patel <anup.patel@wdc.com>
We define a CPU feature for AIA CSR support in RISC-V CPUs which
can be set by machine/device emulation. The RISC-V CSR emulation
will also check this feature for emulating AIA CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 1bdd03731f..d0c1725eaf 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -75,7 +75,8 @@ enum {
RISCV_FEATURE_MMU,
RISCV_FEATURE_PMP,
RISCV_FEATURE_EPMP,
- RISCV_FEATURE_MISA
+ RISCV_FEATURE_MISA,
+ RISCV_FEATURE_AIA
};
#define PRIV_VERSION_1_10_0 0x00011000
--
2.25.1
- [PATCH v6 00/23] QEMU RISC-V AIA support, Anup Patel, 2021/12/30
- [PATCH v6 01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode, Anup Patel, 2021/12/30
- [PATCH v6 02/23] target/riscv: Implement SGEIP bit in hip and hie CSRs, Anup Patel, 2021/12/30
- [PATCH v6 03/23] target/riscv: Implement hgeie and hgeip CSRs, Anup Patel, 2021/12/30
- [PATCH v6 04/23] target/riscv: Improve delivery of guest external interrupts, Anup Patel, 2021/12/30
- [PATCH v6 05/23] target/riscv: Allow setting CPU feature from machine/device emulation, Anup Patel, 2021/12/30
- [PATCH v6 06/23] target/riscv: Add AIA cpu feature,
Anup Patel <=
- [PATCH v6 07/23] target/riscv: Add defines for AIA CSRs, Anup Patel, 2021/12/30
- [PATCH v6 09/23] target/riscv: Implement AIA local interrupt priorities, Anup Patel, 2021/12/30
- [PATCH v6 10/23] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32, Anup Patel, 2021/12/30
- [PATCH v6 11/23] target/riscv: Implement AIA hvictl and hviprioX CSRs, Anup Patel, 2021/12/30
- [PATCH v6 12/23] target/riscv: Implement AIA interrupt filtering CSRs, Anup Patel, 2021/12/30
- [PATCH v6 13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs, Anup Patel, 2021/12/30
- [PATCH v6 14/23] target/riscv: Implement AIA xiselect and xireg CSRs, Anup Patel, 2021/12/30
- [PATCH v6 15/23] target/riscv: Implement AIA IMSIC interface CSRs, Anup Patel, 2021/12/30
- [PATCH v6 16/23] hw/riscv: virt: Use AIA INTC compatible string when available, Anup Patel, 2021/12/30
- [PATCH v6 17/23] target/riscv: Allow users to force enable AIA CSRs in HART, Anup Patel, 2021/12/30