On Thu, 16 Dec 2021 14:16:57 +0100
Nico Boehr <nrb@linux.ibm.com> wrote:
Previously, we required bits 5, 6 and 7 to be zero (0x07 == 0b111). But,
as per the principles of operation, bit 5 is ignored in MSCH and bits 0,
1, 6 and 7 need to be zero.
On a second thought, don't we have to make sure then that bit 5 is
ignored?
static void copy_pmcw_from_guest(PMCW *dest, const PMCW *src)
{
int i;
dest->intparm = be32_to_cpu(src->intparm);
dest->flags = be16_to_cpu(src->flags);
dest->devno = be16_to_cpu(src->devno);
Here we seem to grab flags as a whole, but actually we would have to
mask of bit 5.
I can spin a patch myself, provided we agree on that this needs to be
fixed, but, it would probably be better to have the two changes in one
patch.
Regards,
Halil
As both PMCW_FLAGS_MASK_INVALID and ioinst_schib_valid() are only used
by ioinst_handle_msch(), adjust the mask accordingly.
Fixes: db1c8f53bfb1 ("s390: Channel I/O basic definitions.")
Signed-off-by: Nico Boehr <nrb@linux.ibm.com>
Reviewed-by: Pierre Morel <pmorel@linux.ibm.com>
Reviewed-by: Halil Pasic <pasic@linux.ibm.com>
Reviewed-by: Janosch Frank <frankja@linux.ibm.com>