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[PULL 022/101] softfloat: Add flag specific to Inf * 0
From: |
Cédric Le Goater |
Subject: |
[PULL 022/101] softfloat: Add flag specific to Inf * 0 |
Date: |
Thu, 16 Dec 2021 21:24:55 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
PowerPC has this flag, and it's easier to compute it here
than after the fact.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-4-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/fpu/softfloat-types.h | 1 +
fpu/softfloat-parts.c.inc | 4 ++--
fpu/softfloat-specialize.c.inc | 12 ++++++------
3 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
index eaa12e1e0033..56b4cf783544 100644
--- a/include/fpu/softfloat-types.h
+++ b/include/fpu/softfloat-types.h
@@ -153,6 +153,7 @@ enum {
float_flag_input_denormal = 0x0020,
float_flag_output_denormal = 0x0040,
float_flag_invalid_isi = 0x0080, /* inf - inf */
+ float_flag_invalid_imz = 0x0100, /* inf * 0 */
};
/*
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
index eb2b475ca466..3ed793347b18 100644
--- a/fpu/softfloat-parts.c.inc
+++ b/fpu/softfloat-parts.c.inc
@@ -423,7 +423,7 @@ static FloatPartsN *partsN(mul)(FloatPartsN *a, FloatPartsN
*b,
/* Inf * Zero == NaN */
if (unlikely(ab_mask == float_cmask_infzero)) {
- float_raise(float_flag_invalid, s);
+ float_raise(float_flag_invalid | float_flag_invalid_imz, s);
parts_default_nan(a, s);
return a;
}
@@ -489,6 +489,7 @@ static FloatPartsN *partsN(muladd)(FloatPartsN *a,
FloatPartsN *b,
if (unlikely(ab_mask != float_cmask_normal)) {
if (unlikely(ab_mask == float_cmask_infzero)) {
+ float_raise(float_flag_invalid | float_flag_invalid_imz, s);
goto d_nan;
}
@@ -567,7 +568,6 @@ static FloatPartsN *partsN(muladd)(FloatPartsN *a,
FloatPartsN *b,
goto finish_sign;
d_nan:
- float_raise(float_flag_invalid, s);
parts_default_nan(a, s);
return a;
}
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
index f2ad0f335e63..943e3301d209 100644
--- a/fpu/softfloat-specialize.c.inc
+++ b/fpu/softfloat-specialize.c.inc
@@ -506,7 +506,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass
b_cls, FloatClass c_cls,
* the default NaN
*/
if (infzero && is_qnan(c_cls)) {
- float_raise(float_flag_invalid, status);
+ float_raise(float_flag_invalid | float_flag_invalid_imz, status);
return 3;
}
@@ -533,7 +533,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass
b_cls, FloatClass c_cls,
* case sets InvalidOp and returns the default NaN
*/
if (infzero) {
- float_raise(float_flag_invalid, status);
+ float_raise(float_flag_invalid | float_flag_invalid_imz, status);
return 3;
}
/* Prefer sNaN over qNaN, in the a, b, c order. */
@@ -556,7 +556,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass
b_cls, FloatClass c_cls,
* case sets InvalidOp and returns the input value 'c'
*/
if (infzero) {
- float_raise(float_flag_invalid, status);
+ float_raise(float_flag_invalid | float_flag_invalid_imz, status);
return 2;
}
/* Prefer sNaN over qNaN, in the c, a, b order. */
@@ -580,7 +580,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass
b_cls, FloatClass c_cls,
* a default NaN
*/
if (infzero) {
- float_raise(float_flag_invalid, status);
+ float_raise(float_flag_invalid | float_flag_invalid_imz, status);
return 2;
}
@@ -597,7 +597,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass
b_cls, FloatClass c_cls,
#elif defined(TARGET_RISCV)
/* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */
if (infzero) {
- float_raise(float_flag_invalid, status);
+ float_raise(float_flag_invalid | float_flag_invalid_imz, status);
}
return 3; /* default NaN */
#elif defined(TARGET_XTENSA)
@@ -606,7 +606,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass
b_cls, FloatClass c_cls,
* an input NaN if we have one (ie c).
*/
if (infzero) {
- float_raise(float_flag_invalid, status);
+ float_raise(float_flag_invalid | float_flag_invalid_imz, status);
return 2;
}
if (status->use_first_nan) {
--
2.31.1
- [PULL 052/101] target/ppc: Update fres to new flags and float64r32, (continued)
- [PULL 052/101] target/ppc: Update fres to new flags and float64r32, Cédric Le Goater, 2021/12/16
- [PULL 061/101] ppc/ppc405: Change kernel load address, Cédric Le Goater, 2021/12/16
- [PULL 053/101] target/ppc: Use helper_todouble/tosingle in helper_xststdcsp, Cédric Le Goater, 2021/12/16
- [PULL 068/101] ppc/ppc405: Remove flash support, Cédric Le Goater, 2021/12/16
- [PULL 077/101] target/ppc: fix xscvqpdp register access, Cédric Le Goater, 2021/12/16
- [PULL 038/101] target/ppc: Split out do_fmadd, Cédric Le Goater, 2021/12/16
- [PULL 040/101] target/ppc: Split out do_frsp, Cédric Le Goater, 2021/12/16
- [PULL 041/101] target/ppc: Update do_frsp for new flags, Cédric Le Goater, 2021/12/16
- [PULL 044/101] target/ppc: Update xsrqpi and xsrqpxp to new flags, Cédric Le Goater, 2021/12/16
- [PULL 045/101] target/ppc: Update fre to new flags, Cédric Le Goater, 2021/12/16
- [PULL 022/101] softfloat: Add flag specific to Inf * 0,
Cédric Le Goater <=
- [PULL 032/101] target/ppc: Fix VXCVI return value, Cédric Le Goater, 2021/12/16
- [PULL 043/101] target/ppc: Update sqrt for new flags, Cédric Le Goater, 2021/12/16
- [PULL 050/101] target/ppc: Add helper for fmuls, Cédric Le Goater, 2021/12/16
- [PULL 047/101] target/ppc: Add helpers for fmadds et al, Cédric Le Goater, 2021/12/16
- [PULL 054/101] target/ppc: Disable software TLB for the 7450 family, Cédric Le Goater, 2021/12/16
- [PULL 060/101] target/ppc: remove 401/403 CPUs, Cédric Le Goater, 2021/12/16
- [PULL 062/101] ppc: Mark the 'taihu' machine as deprecated, Cédric Le Goater, 2021/12/16
- [PULL 064/101] ppc/ppc405: Convert printfs to trace-events, Cédric Le Goater, 2021/12/16
- [PULL 058/101] target/ppc: Remove 603e exception model, Cédric Le Goater, 2021/12/16
- [PULL 080/101] Revert "target/ppc: Move SPR_DSISR setting to powerpc_excp", Cédric Le Goater, 2021/12/16