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[PULL 080/102] Revert "target/ppc: Move SPR_DSISR setting to powerpc_exc
From: |
Cédric Le Goater |
Subject: |
[PULL 080/102] Revert "target/ppc: Move SPR_DSISR setting to powerpc_excp" |
Date: |
Wed, 15 Dec 2021 18:03:35 +0100 |
From: Fabiano Rosas <farosas@linux.ibm.com>
This reverts commit 336e91f85332dda0ede4c1d15b87a19a0fb898a2.
It breaks the --disable-tcg build:
../target/ppc/excp_helper.c:463:29: error: implicit declaration of
function ‘cpu_ldl_code’ [-Werror=implicit-function-declaration]
We should not have TCG code in powerpc_excp because some kvm-only
routines use it indirectly to dispatch interrupts. See
kvm_handle_debug, spapr_mce_req_event and
spapr_do_system_reset_on_cpu.
We can re-introduce the change once we have split the interrupt
injection code between KVM and TCG.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20211209173323.2166642-1-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/excp_helper.c | 21 ++++++++++++---------
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index feb3fd42e26c..6ba0840e9935 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -464,15 +464,13 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
excp_model, int excp)
break;
}
case POWERPC_EXCP_ALIGN: /* Alignment exception */
+ /* Get rS/rD and rA from faulting opcode */
/*
- * Get rS/rD and rA from faulting opcode.
- * Note: We will only invoke ALIGN for atomic operations,
- * so all instructions are X-form.
+ * Note: the opcode fields will not be set properly for a
+ * direct store load/store, but nobody cares as nobody
+ * actually uses direct store segments.
*/
- {
- uint32_t insn = cpu_ldl_code(env, env->nip);
- env->spr[SPR_DSISR] |= (insn & 0x03FF0000) >> 16;
- }
+ env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
break;
case POWERPC_EXCP_PROGRAM: /* Program exception */
switch (env->error_code & ~0xF) {
@@ -1441,6 +1439,11 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr
vaddr,
int mmu_idx, uintptr_t retaddr)
{
CPUPPCState *env = cs->env_ptr;
+ uint32_t insn;
+
+ /* Restore state and reload the insn we executed, for filling in DSISR. */
+ cpu_restore_state(cs, retaddr, true);
+ insn = cpu_ldl_code(env, env->nip);
switch (env->mmu_model) {
case POWERPC_MMU_SOFT_4xx:
@@ -1456,8 +1459,8 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr
vaddr,
}
cs->exception_index = POWERPC_EXCP_ALIGN;
- env->error_code = 0;
- cpu_loop_exit_restore(cs, retaddr);
+ env->error_code = insn & 0x03FF0000;
+ cpu_loop_exit(cs);
}
#endif /* CONFIG_TCG */
#endif /* !CONFIG_USER_ONLY */
--
2.31.1
- [PULL 067/102] ppc/ppc405: Add some address space definitions, (continued)
- [PULL 067/102] ppc/ppc405: Add some address space definitions, Cédric Le Goater, 2021/12/15
- [PULL 070/102] ppc/ppc405: Introduce ppc405_set_default_bootinfo(), Cédric Le Goater, 2021/12/15
- [PULL 075/102] target/ppc: Fix xs{max, min}[cj]dp to use VSX registers, Cédric Le Goater, 2021/12/15
- [PULL 065/102] ppc/ppc405: Drop flag parameter in ppc405_set_bootinfo(), Cédric Le Goater, 2021/12/15
- [PULL 071/102] ppc/ppc405: Fix boot from kernel, Cédric Le Goater, 2021/12/15
- [PULL 078/102] target/ppc: move xscvqpdp to decodetree, Cédric Le Goater, 2021/12/15
- [PULL 082/102] target/ppc: introduce PMUEventType and PMU overflow timers, Cédric Le Goater, 2021/12/15
- [PULL 084/102] target/ppc: PMU: update counters on PMCs r/w, Cédric Le Goater, 2021/12/15
- [PULL 086/102] target/ppc: enable PMU counter overflow with cycle events, Cédric Le Goater, 2021/12/15
- [PULL 085/102] target/ppc: PMU: update counters on MMCR1 write, Cédric Le Goater, 2021/12/15
- [PULL 080/102] Revert "target/ppc: Move SPR_DSISR setting to powerpc_excp",
Cédric Le Goater <=
- [PULL 072/102] ppc/ppc405: Change default PLL values at reset, Cédric Le Goater, 2021/12/15
- [PULL 077/102] target/ppc: fix xscvqpdp register access, Cédric Le Goater, 2021/12/15
- [PULL 091/102] ppc/pnv: Use the chip class to check the index of PHB3 devices, Cédric Le Goater, 2021/12/15
- [PULL 079/102] target/ppc: Fix e6500 boot, Cédric Le Goater, 2021/12/15
- [PULL 099/102] ppc/pnv: Compute the PHB index from the PHB4 PEC model, Cédric Le Goater, 2021/12/15
- [PULL 097/102] ppc/pnv: Introduce a "chip" property under the PHB4 model, Cédric Le Goater, 2021/12/15
- [PULL 088/102] target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event, Cédric Le Goater, 2021/12/15
- [PULL 096/102] ppc/pnv: Introduce version and device_id class atributes for PHB4 devices, Cédric Le Goater, 2021/12/15
- [PULL 094/102] ppc/pnv: Use QOM hierarchy to scan PHB3 devices, Cédric Le Goater, 2021/12/15
- [PULL 090/102] ppc/pnv: Introduce a "chip" property under PHB3, Cédric Le Goater, 2021/12/15