[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v2 for 6.2?] gicv3: fix ICH_MISR's LRENP computation
From: |
Philippe Mathieu-Daudé |
Subject: |
Re: [PATCH v2 for 6.2?] gicv3: fix ICH_MISR's LRENP computation |
Date: |
Tue, 7 Dec 2021 13:45:30 +0100 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.3.0 |
On 12/7/21 10:44, Damien Hedde wrote:
> According to the "Arm Generic Interrupt Controller Architecture
> Specification GIC architecture version 3 and 4" (version G: page 345
> for aarch64 or 509 for aarch32):
> LRENP bit of ICH_MISR is set when ICH_HCR.LRENPIE==1 and
> ICH_HCR.EOIcount is non-zero.
>
> When only LRENPIE was set (and EOI count was zero), the LRENP bit was
> wrongly set and MISR value was wrong.
>
> As an additional consequence, if an hypervisor set ICH_HCR.LRENPIE,
> the maintenance interrupt was constantly fired. It happens since patch
> 9cee1efe92 ("hw/intc: Set GIC maintenance interrupt level to only 0 or 1")
> which fixed another bug about maintenance interrupt (most significant
> bits of misr, including this one, were ignored in the interrupt trigger).
>
> Fixes: 83f036fe3d ("hw/intc/arm_gicv3: Add accessors for ICH_ system
> registers")
This commit predates 6.1 release, so technically this is not
a regression for 6.2.
> Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
> ---
> The gic doc is available here:
> https://developer.arm.com/documentation/ihi0069/g
>
> v2: identical resend because subject screw-up (sorry)
>
> Thanks,
> Damien
> ---
> hw/intc/arm_gicv3_cpuif.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
> index 7fba931450..85fc369e55 100644
> --- a/hw/intc/arm_gicv3_cpuif.c
> +++ b/hw/intc/arm_gicv3_cpuif.c
> @@ -351,7 +351,8 @@ static uint32_t maintenance_interrupt_state(GICv3CPUState
> *cs)
> /* Scan list registers and fill in the U, NP and EOI bits */
> eoi_maintenance_interrupt_state(cs, &value);
>
> - if (cs->ich_hcr_el2 & (ICH_HCR_EL2_LRENPIE | ICH_HCR_EL2_EOICOUNT_MASK))
> {
> + if ((cs->ich_hcr_el2 & ICH_HCR_EL2_LRENPIE) &&
> + (cs->ich_hcr_el2 & ICH_HCR_EL2_EOICOUNT_MASK)) {
> value |= ICH_MISR_EL2_LRENP;
> }
>
>
- [PATCH v2 for 6.2?] gicv3: fix ICH_MISR's LRENP computation, Damien Hedde, 2021/12/07
- Re: [PATCH v2 for 6.2?] gicv3: fix ICH_MISR's LRENP computation,
Philippe Mathieu-Daudé <=
- Re: [PATCH v2 for 6.2?] gicv3: fix ICH_MISR's LRENP computation, Peter Maydell, 2021/12/07
- RE: [PATCH v2 for 6.2?] gicv3: fix ICH_MISR's LRENP computation, Brian Cain, 2021/12/07
- Re: [PATCH v2 for 6.2?] gicv3: fix ICH_MISR's LRENP computation, Peter Maydell, 2021/12/07
- RE: [PATCH v2 for 6.2?] gicv3: fix ICH_MISR's LRENP computation, Brian Cain, 2021/12/07
- Re: [PATCH v2 for 6.2?] gicv3: fix ICH_MISR's LRENP computation, Peter Maydell, 2021/12/07
- Re: [PATCH v2 for 6.2?] gicv3: fix ICH_MISR's LRENP computation, Damien Hedde, 2021/12/07
- Re: [PATCH v2 for 6.2?] gicv3: fix ICH_MISR's LRENP computation, Peter Maydell, 2021/12/07
Re: [PATCH v2 for 6.2?] gicv3: fix ICH_MISR's LRENP computation, Damien Hedde, 2021/12/07