[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[RFC PATCH v3 16/27] hw/loongarch: Add LoongArch cpu interrupt support(C
From: |
Xiaojuan Yang |
Subject: |
[RFC PATCH v3 16/27] hw/loongarch: Add LoongArch cpu interrupt support(CPUINTC) |
Date: |
Sat, 4 Dec 2021 20:07:14 +0800 |
Loongson-3A5000 support 14 interrupts from 64 - 77(Timer->75 IPI->76)
Loongson-3A5000 and ls7a form a legacy model and extended model irq
hierarchy.Tcg mode emulate a simplified extended model which
has no Legacy I/O Interrupt Controller(LIOINTC) and LPC.
e.g:
| +-----+ +---------+ +-------+ |
| | IPI |--> | CPUINTC | <-- | Timer | |
| +-----+ +---------+ +-------+ |
| ^ |
| | |
| +---------+
| | EIOINTC |
| +---------+
| ^ ^ |
| | | |
| +---------+ +---------+ |
| | PCH-PIC | | PCH-MSI | |
| +---------+ +---------+ |
| ^ ^ ^ |
| | | | |
| +---------+ +---------+ +---------+ |
| | UARTs | | Devices | | Devices | |
| +---------+ +---------+ +---------+ |
| ^ |
The following series patch will realize the interrupt
controller in this model.
More detailed info can be found at the kernel doc or manual
1.https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/
linux-loongson.git/tree/Documentation/loongarch?h=loongarch-next
2.https://github.com/loongson/LoongArch-Documentation
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/cpu.c | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 62c2a4d813..afa550c950 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -504,11 +504,39 @@ static void loongarch_cpu_realizefn(DeviceState *dev,
Error **errp)
lacc->parent_realize(dev, errp);
}
+#ifndef CONFIG_USER_ONLY
+static void loongarch_cpu_set_irq(void *opaque, int irq, int level)
+{
+ LoongArchCPU *cpu = opaque;
+ CPULoongArchState *env = &cpu->env;
+ CPUState *cs = CPU(cpu);
+
+ if (irq < 0 || irq > N_IRQS) {
+ return;
+ }
+
+ if (level) {
+ env->CSR_ESTAT |= 1 << irq;
+ } else {
+ env->CSR_ESTAT &= ~(1 << irq);
+ }
+
+ if (FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS)) {
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
+ } else {
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
+ }
+}
+#endif
+
static void loongarch_cpu_initfn(Object *obj)
{
LoongArchCPU *cpu = LOONGARCH_CPU(obj);
cpu_set_cpustate_pointers(cpu);
+#ifndef CONFIG_USER_ONLY
+ qdev_init_gpio_in(DEVICE(cpu), loongarch_cpu_set_irq, N_IRQS);
+#endif
}
static ObjectClass *loongarch_cpu_class_by_name(const char *cpu_model)
--
2.27.0
- [RFC PATCH v3 18/27] hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC), (continued)
- [RFC PATCH v3 26/27] hw/loongarch: Add LoongArch smbios support, Xiaojuan Yang, 2021/12/04
- [RFC PATCH v3 27/27] hw/loongarch: Add LoongArch acpi support, Xiaojuan Yang, 2021/12/04
- [RFC PATCH v3 25/27] hw/loongarch: Add -kernel and -initrd options support, Xiaojuan Yang, 2021/12/04
- [RFC PATCH v3 23/27] hw/loongarch: Add LoongArch ls7a rtc device support, Xiaojuan Yang, 2021/12/04
- [RFC PATCH v3 13/27] target/loongarch: Add gdb support., Xiaojuan Yang, 2021/12/04
- [RFC PATCH v3 16/27] hw/loongarch: Add LoongArch cpu interrupt support(CPUINTC),
Xiaojuan Yang <=
- [RFC PATCH v3 07/27] target/loongarch: Add LoongArch CSR instruction, Xiaojuan Yang, 2021/12/04
- [RFC PATCH v3 06/27] target/loongarch: Add MMU support for LoongArch CPU., Xiaojuan Yang, 2021/12/04
- [RFC PATCH v3 08/27] target/loongarch: Add LoongArch IOCSR instruction, Xiaojuan Yang, 2021/12/04
- [RFC PATCH v3 02/27] target/loongarch: Add CSR registers definition, Xiaojuan Yang, 2021/12/04
- Re: [RFC PATCH v3 00/27] Add LoongArch softmmu support., yangxiaojuan, 2021/12/12