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[RFC PATCH v3 19/27] hw/intc: Add LoongArch ls7a msi interrupt controlle
From: |
Xiaojuan Yang |
Subject: |
[RFC PATCH v3 19/27] hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI) |
Date: |
Sat, 4 Dec 2021 20:07:17 +0800 |
This patch realize PCH-MSI interrupt controller.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
hw/intc/Kconfig | 5 +++
hw/intc/loongarch_pch_msi.c | 67 +++++++++++++++++++++++++++++
hw/intc/meson.build | 1 +
hw/intc/trace-events | 3 ++
hw/loongarch/Kconfig | 1 +
include/hw/intc/loongarch_pch_msi.h | 21 +++++++++
6 files changed, 98 insertions(+)
create mode 100644 hw/intc/loongarch_pch_msi.c
create mode 100644 include/hw/intc/loongarch_pch_msi.h
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index 96da13ad1d..dc5f41f5f5 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -80,3 +80,8 @@ config LOONGARCH_IPI
config LOONGARCH_PCH_PIC
bool
select UNIMP
+
+config LOONGARCH_PCH_MSI
+ select MSI_NONBROKEN
+ bool
+ select UNIMP
diff --git a/hw/intc/loongarch_pch_msi.c b/hw/intc/loongarch_pch_msi.c
new file mode 100644
index 0000000000..c7777f763b
--- /dev/null
+++ b/hw/intc/loongarch_pch_msi.c
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * QEMU Loongson 7A1000 msi interrupt controller.
+ *
+ * Copyright (C) 2021 Loongson Technology Corporation Limited
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "hw/irq.h"
+#include "hw/intc/loongarch_pch_msi.h"
+#include "hw/intc/loongarch_pch_pic.h"
+#include "hw/pci/msi.h"
+#include "hw/misc/unimp.h"
+#include "migration/vmstate.h"
+#include "trace.h"
+
+static uint64_t loongarch_msi_mem_read(void *opaque, hwaddr addr, unsigned
size)
+{
+ return 0;
+}
+
+static void loongarch_msi_mem_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size)
+{
+ loongarch_pch_msi *s = LOONGARCH_PCH_MSI(opaque);
+ int irq_num = val & 0xff;
+
+ trace_loongarch_msi_set_irq(irq_num);
+ qemu_set_irq(s->pch_msi_irq[irq_num - PCH_PIC_IRQ_NUM], 1);
+}
+
+static const MemoryRegionOps loongarch_pch_msi_ops = {
+ .read = loongarch_msi_mem_read,
+ .write = loongarch_msi_mem_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void loongarch_pch_msi_init(Object *obj)
+{
+ loongarch_pch_msi *s = LOONGARCH_PCH_MSI(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ int i;
+
+ memory_region_init_io(&s->msi_mmio, obj, &loongarch_pch_msi_ops,
+ s, TYPE_LOONGARCH_PCH_MSI, 0x8);
+ sysbus_init_mmio(sbd, &s->msi_mmio);
+ msi_nonbroken = true;
+
+ for (i = 0; i < PCH_MSI_IRQ_NUM; i++) {
+ sysbus_init_irq(sbd, &s->pch_msi_irq[i]);
+ }
+}
+
+static const TypeInfo loongarch_pch_msi_info = {
+ .name = TYPE_LOONGARCH_PCH_MSI,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(loongarch_pch_msi),
+ .instance_init = loongarch_pch_msi_init,
+};
+
+static void loongarch_pch_msi_register_types(void)
+{
+ type_register_static(&loongarch_pch_msi_info);
+}
+
+type_init(loongarch_pch_msi_register_types)
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index 33ba63266e..acefe0c5aa 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -59,3 +59,4 @@ specific_ss.add(when: 'CONFIG_GOLDFISH_PIC', if_true:
files('goldfish_pic.c'))
specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c'))
specific_ss.add(when: 'CONFIG_LOONGARCH_IPI', if_true:
files('loongarch_ipi.c'))
specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true:
files('loongarch_pch_pic.c'))
+specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_MSI', if_true:
files('loongarch_pch_msi.c'))
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index 52fedf82be..20da343cfe 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -255,3 +255,6 @@ loongarch_ipi_write(unsigned size, uint32_t addr, unsigned
long val) "size: %u a
pch_pic_irq_handler(uint32_t edge, int irq, int level) "edge 0x%02x irq %d
level %d"
loongarch_pch_pic_read(unsigned size, uint32_t addr, unsigned long val) "size:
%u addr: 0x%"PRIx32 "val: 0x%" PRIx64
loongarch_pch_pic_write(unsigned size, uint32_t addr, unsigned long val)
"size: %u addr: 0x%"PRIx32 "val: 0x%" PRIx64
+
+# loongarch_pch_msi.c
+loongarch_msi_set_irq(int irq_num) "set msi irq %d"
diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig
index c2b8046b94..cd38d03a19 100644
--- a/hw/loongarch/Kconfig
+++ b/hw/loongarch/Kconfig
@@ -3,3 +3,4 @@ config LOONGSON3_LS7A
select PCI_EXPRESS_7A
select LOONGARCH_IPI
select LOONGARCH_PCH_PIC
+ select LOONGARCH_PCH_MSI
diff --git a/include/hw/intc/loongarch_pch_msi.h
b/include/hw/intc/loongarch_pch_msi.h
new file mode 100644
index 0000000000..35297d51d8
--- /dev/null
+++ b/include/hw/intc/loongarch_pch_msi.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * LoongArch 7A1000 I/O interrupt controller definitions
+ *
+ * Copyright (C) 2021 Loongson Technology Corporation Limited
+ */
+
+#define TYPE_LOONGARCH_PCH_MSI "loongarch_pch_msi"
+DECLARE_INSTANCE_CHECKER(struct loongarch_pch_msi, LOONGARCH_PCH_MSI,
+ TYPE_LOONGARCH_PCH_MSI)
+
+/* Msi irq start start from 64 to 255 */
+#define PCH_MSI_IRQ_START 64
+#define PCH_MSI_IRQ_END 255
+#define PCH_MSI_IRQ_NUM 192
+
+typedef struct loongarch_pch_msi {
+ SysBusDevice parent_obj;
+ qemu_irq pch_msi_irq[PCH_MSI_IRQ_NUM];
+ MemoryRegion msi_mmio;
+} loongarch_pch_msi;
--
2.27.0
- [RFC PATCH v3 10/27] target/loongarch: Add other core instructions support, (continued)
- [RFC PATCH v3 10/27] target/loongarch: Add other core instructions support, Xiaojuan Yang, 2021/12/04
- [RFC PATCH v3 14/27] hw/pci-host: Add ls7a1000 PCIe Host bridge support for Loongson3 Platform, Xiaojuan Yang, 2021/12/04
- [RFC PATCH v3 15/27] hw/loongarch: Add support loongson3-ls7a machine type., Xiaojuan Yang, 2021/12/04
- [RFC PATCH v3 17/27] hw/loongarch: Add LoongArch ipi interrupt support(IPI), Xiaojuan Yang, 2021/12/04
- [RFC PATCH v3 19/27] hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI),
Xiaojuan Yang <=
- [RFC PATCH v3 22/27] hw/loongarch: Add some devices support for 3A5000., Xiaojuan Yang, 2021/12/04
- [RFC PATCH v3 21/27] hw/loongarch: Add irq hierarchy for the system, Xiaojuan Yang, 2021/12/04
- [RFC PATCH v3 20/27] hw/intc: Add LoongArch extioi interrupt controller(EIOINTC), Xiaojuan Yang, 2021/12/04