Re: [PATCH v6 08/18] target/riscv: moving some insns close to similar insns

[Alistair Francis]

On Mon, Nov 29, 2021 at 12:05 AM Frédéric Pétrot
<frederic.petrot@univ-grenoble-alpes.fr> wrote:
>
> lwu and ld are functionally close to the other loads, but were after the
> stores in the source file.
> Similarly, xor was away from or and and by two arithmetic functions, while
> the immediate versions were nicely put together.
> This patch moves the aforementioned loads after lhu, and xor above or,
> where they more logically belong.
>
> Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/insn_trans/trans_rvi.c.inc | 34 ++++++++++++-------------
>  1 file changed, 17 insertions(+), 17 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc 
> b/target/riscv/insn_trans/trans_rvi.c.inc
> index 51607b3d40..710f5e6a85 100644
> --- a/target/riscv/insn_trans/trans_rvi.c.inc
> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> @@ -176,6 +176,18 @@ static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
>      return gen_load(ctx, a, MO_TEUW);
>  }
>
> +static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
> +{
> +    REQUIRE_64BIT(ctx);
> +    return gen_load(ctx, a, MO_TEUL);
> +}
> +
> +static bool trans_ld(DisasContext *ctx, arg_ld *a)
> +{
> +    REQUIRE_64BIT(ctx);
> +    return gen_load(ctx, a, MO_TEUQ);
> +}
> +
>  static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
>  {
>      TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
> @@ -207,18 +219,6 @@ static bool trans_sw(DisasContext *ctx, arg_sw *a)
>      return gen_store(ctx, a, MO_TESL);
>  }
>
> -static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
> -{
> -    REQUIRE_64BIT(ctx);
> -    return gen_load(ctx, a, MO_TEUL);
> -}
> -
> -static bool trans_ld(DisasContext *ctx, arg_ld *a)
> -{
> -    REQUIRE_64BIT(ctx);
> -    return gen_load(ctx, a, MO_TEUQ);
> -}
> -
>  static bool trans_sd(DisasContext *ctx, arg_sd *a)
>  {
>      REQUIRE_64BIT(ctx);
> @@ -317,11 +317,6 @@ static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
>      return gen_arith(ctx, a, EXT_SIGN, gen_sltu);
>  }
>
> -static bool trans_xor(DisasContext *ctx, arg_xor *a)
> -{
> -    return gen_logic(ctx, a, tcg_gen_xor_tl);
> -}
> -
>  static bool trans_srl(DisasContext *ctx, arg_srl *a)
>  {
>      return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl);
> @@ -332,6 +327,11 @@ static bool trans_sra(DisasContext *ctx, arg_sra *a)
>      return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl);
>  }
>
> +static bool trans_xor(DisasContext *ctx, arg_xor *a)
> +{
> +    return gen_logic(ctx, a, tcg_gen_xor_tl);
> +}
> +
>  static bool trans_or(DisasContext *ctx, arg_or *a)
>  {
>      return gen_logic(ctx, a, tcg_gen_or_tl);
> --
> 2.34.0
>
>