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[PATCH v10 01/77] target/riscv: drop vector 0.7.1 and add 1.0 support
From: |
frank . chang |
Subject: |
[PATCH v10 01/77] target/riscv: drop vector 0.7.1 and add 1.0 support |
Date: |
Mon, 29 Nov 2021 11:02:21 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
target/riscv/cpu.c | 16 ++++++++--------
target/riscv/cpu.h | 2 +-
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f7fda686863..c760ea08621 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -523,7 +523,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
ext |= RVH;
}
if (cpu->cfg.ext_v) {
- int vext_version = VEXT_VERSION_0_07_1;
+ int vext_version = VEXT_VERSION_1_00_0;
ext |= RVV;
if (!is_power_of_2(cpu->cfg.vlen)) {
error_setg(errp,
@@ -548,8 +548,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
return;
}
if (cpu->cfg.vext_spec) {
- if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) {
- vext_version = VEXT_VERSION_0_07_1;
+ if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) {
+ vext_version = VEXT_VERSION_1_00_0;
} else {
error_setg(errp,
"Unsupported vector spec version '%s'",
@@ -558,7 +558,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
}
} else {
qemu_log("vector version is not specified, "
- "use the default value v0.7.1\n");
+ "use the default value v1.0\n");
}
set_vext_version(env, vext_version);
}
@@ -626,6 +626,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
+ DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
@@ -635,6 +636,9 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
+ DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
+ DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
+ DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
/* These are experimental so mark with 'x-' */
DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false),
@@ -643,10 +647,6 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false),
DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
- DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
- DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
- DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
- DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
/* ePMP 0.9.3 */
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index ef677f90922..5ea2004ae02 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -81,7 +81,7 @@ enum {
#define PRIV_VERSION_1_10_0 0x00011000
#define PRIV_VERSION_1_11_0 0x00011100
-#define VEXT_VERSION_0_07_1 0x00000701
+#define VEXT_VERSION_1_00_0 0x00010000
enum {
TRANSLATE_SUCCESS,
--
2.25.1
- [PATCH v10 71/77] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11, (continued)
- [PATCH v10 71/77] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11, frank . chang, 2021/11/28
- [PATCH v10 13/77] target/riscv: rvv-1.0: add fractional LMUL, frank . chang, 2021/11/28
- [PATCH v10 72/77] target/riscv: rvv-1.0: add vsetivli instruction, frank . chang, 2021/11/28
- [PATCH v10 73/77] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us(), frank . chang, 2021/11/28
- [PATCH v10 74/77] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns, frank . chang, 2021/11/28
- [PATCH v10 75/77] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm, frank . chang, 2021/11/28
- [PATCH v10 76/77] target/riscv: rvv-1.0: update opivv_vadc_check() comment, frank . chang, 2021/11/28
- [PATCH v10 77/77] target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions, frank . chang, 2021/11/28
- [PATCH v10 15/77] target/riscv: rvv-1.0: update check functions, frank . chang, 2021/11/28
- [PATCH v10 12/77] target/riscv: rvv-1.0: remove MLEN calculations, frank . chang, 2021/11/28
- [PATCH v10 01/77] target/riscv: drop vector 0.7.1 and add 1.0 support,
frank . chang <=
- [PATCH v10 02/77] target/riscv: Use FIELD_EX32() to extract wd field, frank . chang, 2021/11/28
- [PATCH v10 34/77] target/riscv: rvv-1.0: allow load element with sign-extended, frank . chang, 2021/11/28
- [PATCH v10 44/77] target/riscv: rvv-1.0: narrowing integer right shift instructions, frank . chang, 2021/11/28
- [PATCH v10 46/77] target/riscv: rvv-1.0: single-width saturating add and subtract instructions, frank . chang, 2021/11/28