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[PATCH v5 16/22] target/riscv: Adjust vsetvl according to XLEN
From: |
LIU Zhiwei |
Subject: |
[PATCH v5 16/22] target/riscv: Adjust vsetvl according to XLEN |
Date: |
Thu, 25 Nov 2021 15:39:45 +0800 |
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 5 +++++
target/riscv/vector_helper.c | 7 +++++--
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 2cee98f152..ef1d87af38 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -427,6 +427,11 @@ static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
RISCVMXL cpu_get_xl(CPURISCVState *env);
+static inline int riscv_cpu_xlen(CPURISCVState *env)
+{
+ return 16 << env->xl;
+}
+
/*
* A simplification for VLMAX
* = (1 << LMUL) * VLEN / (8 * (1 << SEW))
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index b02ccefa4d..e9d49cf105 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -33,8 +33,11 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong
s1,
RISCVCPU *cpu = env_archcpu(env);
uint16_t sew = 8 << FIELD_EX64(s2, VTYPE, VSEW);
uint8_t ediv = FIELD_EX64(s2, VTYPE, VEDIV);
- bool vill = FIELD_EX64(s2, VTYPE, VILL);
- target_ulong reserved = FIELD_EX64(s2, VTYPE, RESERVED);
+ int xlen = riscv_cpu_xlen(env);
+ bool vill = (s2 >> (xlen - 1)) & 0x1;
+ target_ulong reserved = s2 &
+ MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
+ xlen - 1 - R_VTYPE_RESERVED_SHIFT);
if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved != 0)) {
/* only set vill bit. */
--
2.25.1
- [PATCH v5 07/22] target/riscv: Use gdb xml according to max mxlen, (continued)
- [PATCH v5 07/22] target/riscv: Use gdb xml according to max mxlen, LIU Zhiwei, 2021/11/25
- [PATCH v5 08/22] target/riscv: Relax debug check for pm write, LIU Zhiwei, 2021/11/25
- [PATCH v5 09/22] target/riscv: Adjust csr write mask with XLEN, LIU Zhiwei, 2021/11/25
- [PATCH v5 10/22] target/riscv: Create current pm fields in env, LIU Zhiwei, 2021/11/25
- [PATCH v5 11/22] target/riscv: Alloc tcg global for cur_pm[mask|base], LIU Zhiwei, 2021/11/25
- [PATCH v5 12/22] target/riscv: Calculate address according to XLEN, LIU Zhiwei, 2021/11/25
- [PATCH v5 13/22] target/riscv: Split pm_enabled into mask and base, LIU Zhiwei, 2021/11/25
- [PATCH v5 14/22] target/riscv: Split out the vill from vtype, LIU Zhiwei, 2021/11/25
- [PATCH v5 15/22] target/riscv: Fix RESERVED field length in VTYPE, LIU Zhiwei, 2021/11/25
- [PATCH v5 16/22] target/riscv: Adjust vsetvl according to XLEN,
LIU Zhiwei <=
- [PATCH v5 17/22] target/riscv: Remove VILL field in VTYPE, LIU Zhiwei, 2021/11/25
- [PATCH v5 18/22] target/riscv: Ajdust vector atomic check with XLEN, LIU Zhiwei, 2021/11/25
- [PATCH v5 19/22] target/riscv: Fix check range for first fault only, LIU Zhiwei, 2021/11/25
- [PATCH v5 20/22] target/riscv: Adjust vector address with mask, LIU Zhiwei, 2021/11/25
- [PATCH v5 21/22] target/riscv: Adjust scalar reg in vector with XLEN, LIU Zhiwei, 2021/11/25
- [PATCH v5 22/22] target/riscv: Enable uxl field write, LIU Zhiwei, 2021/11/25