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Re: [PATCH v4 06/20] target/riscv: Relax debug check for pm write
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v4 06/20] target/riscv: Relax debug check for pm write |
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Date: |
Tue, 16 Nov 2021 13:13:15 +1000 |
On Fri, Nov 12, 2021 at 2:12 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/csr.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 9f41954894..74c0b788fd 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1445,6 +1445,9 @@ static bool check_pm_current_disabled(CPURISCVState
> *env, int csrno)
> int csr_priv = get_field(csrno, 0x300);
> int pm_current;
>
> + if (env->debugger) {
> + return false;
> + }
> /*
> * If priv lvls differ that means we're accessing csr from higher priv
> lvl,
> * so allow the access
> --
> 2.25.1
>
>
- Re: [PATCH v4 01/20] target/riscv: Don't save pc when exception return, (continued)
- [PATCH v4 02/20] target/riscv: Sign extend pc for different XLEN, LIU Zhiwei, 2021/11/11
- [PATCH v4 03/20] target/riscv: Ignore the pc bits above XLEN, LIU Zhiwei, 2021/11/11
- [PATCH v4 04/20] target/riscv: Extend pc for runtime pc write, LIU Zhiwei, 2021/11/11
- [PATCH v4 05/20] target/riscv: Use gdb xml according to max mxlen, LIU Zhiwei, 2021/11/11
- [PATCH v4 06/20] target/riscv: Relax debug check for pm write, LIU Zhiwei, 2021/11/11
- Re: [PATCH v4 06/20] target/riscv: Relax debug check for pm write,
Alistair Francis <=
- [PATCH v4 07/20] target/riscv: Adjust csr write mask with XLEN, LIU Zhiwei, 2021/11/11
- [PATCH v4 08/20] target/riscv: Create current pm fields in env, LIU Zhiwei, 2021/11/11
- [PATCH v4 09/20] target/riscv: Alloc tcg global for cur_pm[mask|base], LIU Zhiwei, 2021/11/11
- [PATCH v4 10/20] target/riscv: Calculate address according to XLEN, LIU Zhiwei, 2021/11/11
- [PATCH v4 11/20] target/riscv: Split pm_enabled into mask and base, LIU Zhiwei, 2021/11/11