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Re: [PATCH] arm: Don't remove EL3 exposure for SMC conduit

From: Peter Maydell
Subject: Re: [PATCH] arm: Don't remove EL3 exposure for SMC conduit
Date: Mon, 15 Nov 2021 10:46:30 +0000

On Sun, 14 Nov 2021 at 17:41, Alexander Graf <agraf@csgraf.de> wrote:
> > Am 14.11.2021 um 18:20 schrieb Peter Maydell <peter.maydell@linaro.org>:
> > This is tricky, because we use the cpu->isar values to determine whether
> > we should be emulating things. So this change means we now create an
> > inconsistent CPU which in some ways claims to have EL3 (the ISAR ID
> > bits say so) and in some ways does not (the ARM_FEATURE_EL3 flag is
> > unset), and depending on which of the two "do we have EL3?" methods
> > any bit of the TCG code is using will give different results...
> Do you think it would be sufficient to go through all readers of the isar 
> bits and guard them behind an ARM_FEATURE_EL3 check in addition? I'll be 
> happy to do so then! :)

That would be a big reverse-course on a design choice we made that
the preference is to look at the ID registers and phase out the
use of ARM_FEATURE bits where possible.

-- PMM

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