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[PATCH v2 12/30] target/loongarch: Add timer related instructions suppor
From: |
Xiaojuan Yang |
Subject: |
[PATCH v2 12/30] target/loongarch: Add timer related instructions support. |
Date: |
Tue, 9 Nov 2021 20:51:51 +0800 |
This includes:
-RDTIME{L/H}.W
-RDTIME.D
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/helper.h | 1 +
target/loongarch/insn_trans/trans_extra.c.inc | 32 +++++++++++++++++++
target/loongarch/op_helper.c | 4 +++
target/loongarch/translate.c | 2 ++
4 files changed, 39 insertions(+)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index afb362c9c7..fc4eaa1ce8 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -114,4 +114,5 @@ DEF_HELPER_4(lddir, tl, env, tl, tl, i32)
DEF_HELPER_4(ldpte, void, env, tl, tl, i32)
DEF_HELPER_1(ertn, void, env)
DEF_HELPER_1(idle, void, env)
+DEF_HELPER_1(rdtime_d, i64, env)
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/loongarch/insn_trans/trans_extra.c.inc
b/target/loongarch/insn_trans/trans_extra.c.inc
index 76f0698da7..ab46331547 100644
--- a/target/loongarch/insn_trans/trans_extra.c.inc
+++ b/target/loongarch/insn_trans/trans_extra.c.inc
@@ -33,22 +33,54 @@ static bool trans_asrtgt_d(DisasContext *ctx, arg_asrtgt_d
* a)
return true;
}
+#ifndef CONFIG_USER_ONLY
+static bool gen_rdtime(DisasContext *ctx, arg_rdtimel_w *a,
+ bool word, bool high)
+{
+ TCGv dst1 = gpr_dst(ctx, a->rd, EXT_NONE);
+ TCGv dst2 = gpr_dst(ctx, a->rj, EXT_NONE);
+
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_rdtime_d(dst1, cpu_env);
+ if (word) {
+ tcg_gen_sextract_tl(dst1, dst1, high ? 32 : 0, 32);
+ }
+ tcg_gen_ld_i64(dst2, cpu_env, offsetof(CPULoongArchState, CSR_TMID));
+
+ return true;
+}
+#endif
+
static bool trans_rdtimel_w(DisasContext *ctx, arg_rdtimel_w *a)
{
+#ifdef CONFIG_USER_ONLY
tcg_gen_movi_tl(cpu_gpr[a->rd], 0);
return true;
+#else
+ return gen_rdtime(ctx, a, 1, 0);
+#endif
}
static bool trans_rdtimeh_w(DisasContext *ctx, arg_rdtimeh_w *a)
{
+#ifdef CONFIG_USER_ONLY
tcg_gen_movi_tl(cpu_gpr[a->rd], 0);
return true;
+#else
+ return gen_rdtime(ctx, a, 1, 1);
+#endif
}
static bool trans_rdtime_d(DisasContext *ctx, arg_rdtime_d *a)
{
+#ifdef CONFIG_USER_ONLY
tcg_gen_movi_tl(cpu_gpr[a->rd], 0);
return true;
+#else
+ return gen_rdtime(ctx, a, 0, 0);
+#endif
}
static bool trans_cpucfg(DisasContext *ctx, arg_cpucfg *a)
diff --git a/target/loongarch/op_helper.c b/target/loongarch/op_helper.c
index e2a9fd9ad0..fb47914c87 100644
--- a/target/loongarch/op_helper.c
+++ b/target/loongarch/op_helper.c
@@ -134,5 +134,9 @@ void helper_idle(CPULoongArchState *env)
do_raise_exception(env, EXCP_HLT, 0);
}
+uint64_t helper_rdtime_d(CPULoongArchState *env)
+{
+ return cpu_loongarch_get_stable_counter(env);
+}
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
index 3935b14163..15276a240f 100644
--- a/target/loongarch/translate.c
+++ b/target/loongarch/translate.c
@@ -25,6 +25,8 @@ static TCGv cpu_lladdr, cpu_llval;
TCGv_i32 cpu_fcsr0;
TCGv_i64 cpu_fpr[32];
+#include "exec/gen-icount.h"
+
#define DISAS_STOP DISAS_TARGET_0
#define DISAS_EXIT DISAS_TARGET_1
--
2.27.0
- [PATCH v2 00/30] Add Loongarch softmmu support., Xiaojuan Yang, 2021/11/09
- [PATCH v2 01/30] target/loongarch: Update README, Xiaojuan Yang, 2021/11/09
- [PATCH v2 04/30] target/loongarch: Define exceptions for LoongArch., Xiaojuan Yang, 2021/11/09
- [PATCH v2 02/30] target/loongarch: Add CSR registers definition, Xiaojuan Yang, 2021/11/09
- [PATCH v2 05/30] target/loongarch: Implement qmp_query_cpu_definitions(), Xiaojuan Yang, 2021/11/09
- [PATCH v2 12/30] target/loongarch: Add timer related instructions support.,
Xiaojuan Yang <=
- [PATCH v2 03/30] target/loongarch: Add basic vmstate description of CPU., Xiaojuan Yang, 2021/11/09