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Re: [ PATCH v3 05/10] target/riscv: Implement mcountinhibit CSR
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From: |
Bin Meng |
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Subject: |
Re: [ PATCH v3 05/10] target/riscv: Implement mcountinhibit CSR |
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Date: |
Thu, 4 Nov 2021 19:49:30 +0800 |
On Tue, Oct 26, 2021 at 4:05 AM Atish Patra <atish.patra@wdc.com> wrote:
>
> As per the privilege specification v1.11, mcountinhibit allows to start/stop
> a pmu counter selectively.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> ---
> target/riscv/cpu.h | 2 ++
> target/riscv/cpu_bits.h | 4 ++++
> target/riscv/csr.c | 25 +++++++++++++++++++++++++
> target/riscv/machine.c | 5 +++--
> 4 files changed, 34 insertions(+), 2 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>