[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v4 04/10] target/arm: Split arm_pre_translate_insn
From: |
Richard Henderson |
Subject: |
[PATCH v4 04/10] target/arm: Split arm_pre_translate_insn |
Date: |
Wed, 3 Nov 2021 00:03:46 -0400 |
Create arm_check_ss_active and arm_check_kernelpage.
Reverse the order of the tests. While it doesn't matter in practice,
because only user-only has a kernel page and user-only never sets
ss_active, ss_active has priority over execution exceptions and it
is best to keep them in the proper order.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index a39456ea98..82d4e24c27 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9513,7 +9513,7 @@ static void arm_tr_insn_start(DisasContextBase *dcbase,
CPUState *cpu)
dc->insn_start = tcg_last_op();
}
-static bool arm_pre_translate_insn(DisasContext *dc)
+static bool arm_check_kernelpage(DisasContext *dc)
{
#ifdef CONFIG_USER_ONLY
/* Intercept jump to the magic kernel page. */
@@ -9525,7 +9525,11 @@ static bool arm_pre_translate_insn(DisasContext *dc)
return true;
}
#endif
+ return false;
+}
+static bool arm_check_ss_active(DisasContext *dc)
+{
if (dc->ss_active && !dc->pstate_ss) {
/* Singlestep state is Active-pending.
* If we're in this state at the start of a TB then either
@@ -9562,7 +9566,7 @@ static void arm_tr_translate_insn(DisasContextBase
*dcbase, CPUState *cpu)
uint32_t pc = dc->base.pc_next;
unsigned int insn;
- if (arm_pre_translate_insn(dc)) {
+ if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) {
dc->base.pc_next = pc + 4;
return;
}
@@ -9633,7 +9637,7 @@ static void thumb_tr_translate_insn(DisasContextBase
*dcbase, CPUState *cpu)
uint32_t insn;
bool is_16bit;
- if (arm_pre_translate_insn(dc)) {
+ if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) {
dc->base.pc_next = pc + 2;
return;
}
--
2.25.1
- [PATCH v4 00/10] target/arm: Fix insn exception priorities, Richard Henderson, 2021/11/03
- [PATCH v4 02/10] target/arm: Hoist pc_next to a local variable in arm_tr_translate_insn, Richard Henderson, 2021/11/03
- [PATCH v4 03/10] target/arm: Hoist pc_next to a local variable in thumb_tr_translate_insn, Richard Henderson, 2021/11/03
- [PATCH v4 01/10] target/arm: Hoist pc_next to a local variable in aarch64_tr_translate_insn, Richard Henderson, 2021/11/03
- [PATCH v4 04/10] target/arm: Split arm_pre_translate_insn,
Richard Henderson <=
- [PATCH v4 09/10] target/arm: Suppress bp for exceptions with more priority, Richard Henderson, 2021/11/03
- [PATCH v4 05/10] target/arm: Advance pc for arch single-step exception, Richard Henderson, 2021/11/03
- [PATCH v4 08/10] target/arm: Assert thumb pc is aligned, Richard Henderson, 2021/11/03
- [PATCH v4 06/10] target/arm: Split compute_fsr_fsc out of arm_deliver_fault, Richard Henderson, 2021/11/03
- [PATCH v4 07/10] target/arm: Take an exception if PC is misaligned, Richard Henderson, 2021/11/03
- [PATCH v4 10/10] tests/tcg: Add arm and aarch64 pc alignment tests, Richard Henderson, 2021/11/03