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[PATCH v2 09/30] bsd-user/arm/target_arch_cpu.h: Implement data abort ex
From: |
Warner Losh |
Subject: |
[PATCH v2 09/30] bsd-user/arm/target_arch_cpu.h: Implement data abort exceptions |
Date: |
Tue, 2 Nov 2021 16:52:27 -0600 |
Implement EXCP_PREFETCH_ABORT AND EXCP_DATA_ABORT. Both of these data
exceptions cause a SIGSEGV.
Signed-off-by: Kyle Evans <kevans@FreeBSD.org>
Signed-off-by: Olivier Houchard <cognet@ci0.org>
Signed-off-by: Stacey Son <sson@FreeBSD.org>
Signed-off-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Kyle Evans <kevans@FreeBSD.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
bsd-user/arm/target_arch_cpu.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/bsd-user/arm/target_arch_cpu.h b/bsd-user/arm/target_arch_cpu.h
index 609b78b4e2..cdb9440a65 100644
--- a/bsd-user/arm/target_arch_cpu.h
+++ b/bsd-user/arm/target_arch_cpu.h
@@ -90,6 +90,17 @@ static inline void target_cpu_loop(CPUARMState *env)
case EXCP_INTERRUPT:
/* just indicate that signals should be handled asap */
break;
+ case EXCP_PREFETCH_ABORT:
+ /* See arm/arm/trap.c prefetch_abort_handler() */
+ case EXCP_DATA_ABORT:
+ /* See arm/arm/trap.c data_abort_handler() */
+ info.si_signo = TARGET_SIGSEGV;
+ info.si_errno = 0;
+ /* XXX: check env->error_code */
+ info.si_code = 0;
+ info.si_addr = env->exception.vaddress;
+ queue_signal(env, info.si_signo, &info);
+ break;
case EXCP_DEBUG:
{
--
2.33.0
- [PATCH v2 02/30] bsd-user/arm/target_arch_sysarch.h: Use consistent include guards, (continued)
- [PATCH v2 02/30] bsd-user/arm/target_arch_sysarch.h: Use consistent include guards, Warner Losh, 2021/11/02
- [PATCH v2 03/30] bsd-user/arm/target_syscall.h: Add copyright and update name, Warner Losh, 2021/11/02
- [PATCH v2 04/30] bsd-user/arm/target_arch_cpu.c: Target specific TLS routines, Warner Losh, 2021/11/02
- [PATCH v2 05/30] bsd-user/arm/target_arch_cpu.h: CPU Loop definitions, Warner Losh, 2021/11/02
- [PATCH v2 06/30] bsd-user/arm/target_arch_cpu.h: Implement target_cpu_clone_regs, Warner Losh, 2021/11/02
- [PATCH v2 07/30] bsd-user/arm/target_arch_cpu.h: Dummy target_cpu_loop implementation, Warner Losh, 2021/11/02
- [PATCH v2 08/30] bsd-user/arm/target_arch_cpu.h: Implement trivial EXCP exceptions, Warner Losh, 2021/11/02
- [PATCH v2 09/30] bsd-user/arm/target_arch_cpu.h: Implement data abort exceptions,
Warner Losh <=
- [PATCH v2 10/30] bsd-user/arm/target_arch_cpu.h: Implement system call dispatch, Warner Losh, 2021/11/02
- [PATCH v2 12/30] bsd-user/arm/target_arch_vmparam.h: Parameters for arm address space, Warner Losh, 2021/11/02
- [PATCH v2 11/30] bsd-user/arm/target_arch_reg.h: Implement core dump register copying, Warner Losh, 2021/11/02
- [PATCH v2 14/30] bsd-user/arm/target_arch_thread.h: Routines to create and switch to a thread, Warner Losh, 2021/11/02
- [PATCH v2 13/30] bsd-user/arm/target_arch_sigtramp.h: Signal Trampoline for arm, Warner Losh, 2021/11/02
- [PATCH v2 15/30] bsd-user/arm/target_arch_elf.h: arm defines for ELF, Warner Losh, 2021/11/02
- [PATCH v2 16/30] bsd-user/arm/target_arch_elf.h: arm get hwcap, Warner Losh, 2021/11/02
- [PATCH v2 17/30] bsd-user/arm/target_arch_elf.h: arm get_hwcap2 impl, Warner Losh, 2021/11/02