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Re: [PATCH 09/15] hw/nvme: Implement the Function Level Reset

From: Klaus Jensen
Subject: Re: [PATCH 09/15] hw/nvme: Implement the Function Level Reset
Date: Tue, 2 Nov 2021 15:35:47 +0100

On Oct  7 18:24, Lukasz Maniak wrote:
> From: Łukasz Gieryk <lukasz.gieryk@linux.intel.com>
> This patch implements the FLR, a feature currently not implemented for
> the Nvme device, while listed as a mandatory ("shall") in the 1.4 spec.
> The implementation reuses FLR-related building blocks defined for the
> pci-bridge module, and follows the same logic:
>     - FLR capability is advertised in the PCIE config,
>     - custom pci_write_config callback detects a write to the trigger
>       register and performs the PCI reset,
>     - which, eventually, calls the custom dc->reset handler.
> Depending on reset type, parts of the state should (or should not) be
> cleared. To distinguish the type of reset, an additional parameter is
> passed to the reset function.
> This patch also enables advertisement of the Power Management PCI
> capability. The main reason behind it is to announce the no_soft_reset=1
> bit, to signal SR/IOV support where each VF can be reset individually.
> The implementation purposedly ignores writes to the PMCS.PS register,
> as even such naïve behavior is enough to correctly handle the D3->D0
> transition.
> It’s worth to note, that the power state transition back to to D3, with
> all the corresponding side effects, wasn't and stil isn't handled
> properly.
> Signed-off-by: Łukasz Gieryk <lukasz.gieryk@linux.intel.com>

Reviewed-by: Klaus Jensen <k.jensen@samsung.com>

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