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[PULL 48/60] target/ppc: Move SPR_DSISR setting to powerpc_excp
From: |
Richard Henderson |
Subject: |
[PULL 48/60] target/ppc: Move SPR_DSISR setting to powerpc_excp |
Date: |
Tue, 2 Nov 2021 07:07:28 -0400 |
By doing this while sending the exception, we will have already
done the unwinding, which makes the ppc_cpu_do_unaligned_access
code a bit cleaner.
Update the comment about the expected instruction format.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/excp_helper.c | 21 +++++++++------------
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index b7d1767920..88a8de4b80 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -454,13 +454,15 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
excp_model, int excp)
break;
}
case POWERPC_EXCP_ALIGN: /* Alignment exception */
- /* Get rS/rD and rA from faulting opcode */
/*
- * Note: the opcode fields will not be set properly for a
- * direct store load/store, but nobody cares as nobody
- * actually uses direct store segments.
+ * Get rS/rD and rA from faulting opcode.
+ * Note: We will only invoke ALIGN for atomic operations,
+ * so all instructions are X-form.
*/
- env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
+ {
+ uint32_t insn = cpu_ldl_code(env, env->nip);
+ env->spr[SPR_DSISR] |= (insn & 0x03FF0000) >> 16;
+ }
break;
case POWERPC_EXCP_PROGRAM: /* Program exception */
switch (env->error_code & ~0xF) {
@@ -1462,14 +1464,9 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr
vaddr,
int mmu_idx, uintptr_t retaddr)
{
CPUPPCState *env = cs->env_ptr;
- uint32_t insn;
-
- /* Restore state and reload the insn we executed, for filling in DSISR. */
- cpu_restore_state(cs, retaddr, true);
- insn = cpu_ldl_code(env, env->nip);
cs->exception_index = POWERPC_EXCP_ALIGN;
- env->error_code = insn & 0x03FF0000;
- cpu_loop_exit(cs);
+ env->error_code = 0;
+ cpu_loop_exit_restore(cs, retaddr);
}
#endif
--
2.25.1
- [PULL 29/60] target/microblaze: Make mb_cpu_tlb_fill sysemu only, (continued)
- [PULL 29/60] target/microblaze: Make mb_cpu_tlb_fill sysemu only, Richard Henderson, 2021/11/02
- [PULL 39/60] target/sparc: Make sparc_cpu_tlb_fill sysemu only, Richard Henderson, 2021/11/02
- [PULL 14/60] linux-user/host/mips: Populate host_signal.h, Richard Henderson, 2021/11/02
- [PULL 33/60] target/openrisc: Make openrisc_cpu_tlb_fill sysemu only, Richard Henderson, 2021/11/02
- [PULL 40/60] target/xtensa: Make xtensa_cpu_tlb_fill sysemu only, Richard Henderson, 2021/11/02
- [PULL 42/60] hw/core: Add TCGCPUOps.record_sigbus, Richard Henderson, 2021/11/02
- [PULL 45/60] target/arm: Implement arm_cpu_record_sigbus, Richard Henderson, 2021/11/02
- [PULL 44/60] target/alpha: Implement alpha_cpu_record_sigbus, Richard Henderson, 2021/11/02
- [PULL 43/60] linux-user: Add cpu_loop_exit_sigbus, Richard Henderson, 2021/11/02
- [PULL 46/60] linux-user/hppa: Remove EXCP_UNALIGN handling, Richard Henderson, 2021/11/02
- [PULL 48/60] target/ppc: Move SPR_DSISR setting to powerpc_excp,
Richard Henderson <=
- [PULL 41/60] accel/tcg: Restrict TCGCPUOps::tlb_fill() to sysemu, Richard Henderson, 2021/11/02
- [PULL 47/60] target/microblaze: Do not set MO_ALIGN for user-only, Richard Henderson, 2021/11/02
- [PULL 49/60] target/ppc: Set fault address in ppc_cpu_do_unaligned_access, Richard Henderson, 2021/11/02
- [PULL 50/60] target/ppc: Restrict ppc_cpu_do_unaligned_access to sysemu, Richard Henderson, 2021/11/02
- [PULL 52/60] target/s390x: Implement s390x_cpu_record_sigbus, Richard Henderson, 2021/11/02
- [PULL 54/60] target/sparc: Remove DEBUG_UNALIGNED, Richard Henderson, 2021/11/02
- [PULL 57/60] accel/tcg: Report unaligned atomics for user-only, Richard Henderson, 2021/11/02
- [PULL 56/60] target/sparc: Set fault address in sparc_cpu_do_unaligned_access, Richard Henderson, 2021/11/02
- [PULL 55/60] target/sparc: Split out build_sfsr, Richard Henderson, 2021/11/02
- [PULL 51/60] linux-user/ppc: Remove POWERPC_EXCP_ALIGN handling, Richard Henderson, 2021/11/02