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[PULL 09/12] target/arm: Use the constant variant of store_cpu_field() w
From: |
Richard Henderson |
Subject: |
[PULL 09/12] target/arm: Use the constant variant of store_cpu_field() when possible |
Date: |
Tue, 2 Nov 2021 06:59:31 -0400 |
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
When using a constant variable, we can replace the store_cpu_field()
call by store_cpu_field_constant() which avoid using TCG temporaries.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211029231834.2476117-4-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 21 ++++++---------------
1 file changed, 6 insertions(+), 15 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 083a6d6ed7..52ba562c96 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -364,8 +364,7 @@ void clear_eci_state(DisasContext *s)
* multiple insn executes.
*/
if (s->eci) {
- TCGv_i32 tmp = tcg_const_i32(0);
- store_cpu_field(tmp, condexec_bits);
+ store_cpu_field_constant(0, condexec_bits);
s->eci = 0;
}
}
@@ -740,9 +739,8 @@ void gen_set_condexec(DisasContext *s)
{
if (s->condexec_mask) {
uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1);
- TCGv_i32 tmp = tcg_temp_new_i32();
- tcg_gen_movi_i32(tmp, val);
- store_cpu_field(tmp, condexec_bits);
+
+ store_cpu_field_constant(val, condexec_bits);
}
}
@@ -8362,8 +8360,6 @@ static bool trans_BL(DisasContext *s, arg_i *a)
static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a)
{
- TCGv_i32 tmp;
-
/*
* BLX <imm> would be useless on M-profile; the encoding space
* is used for other insns from v8.1M onward, and UNDEFs before that.
@@ -8377,8 +8373,7 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a)
return false;
}
tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb);
- tmp = tcg_const_i32(!s->thumb);
- store_cpu_field(tmp, thumb);
+ store_cpu_field_constant(!s->thumb, thumb);
gen_jmp(s, (read_pc(s) & ~3) + a->imm);
return true;
}
@@ -8677,7 +8672,6 @@ static bool trans_LCTP(DisasContext *s, arg_LCTP *a)
* doesn't cache branch information, all we need to do is reset
* FPSCR.LTPSIZE to 4.
*/
- TCGv_i32 ltpsize;
if (!dc_isar_feature(aa32_lob, s) ||
!dc_isar_feature(aa32_mve, s)) {
@@ -8688,8 +8682,7 @@ static bool trans_LCTP(DisasContext *s, arg_LCTP *a)
return true;
}
- ltpsize = tcg_const_i32(4);
- store_cpu_field(ltpsize, v7m.ltpsize);
+ store_cpu_field_constant(4, v7m.ltpsize);
return true;
}
@@ -9487,9 +9480,7 @@ static void arm_tr_tb_start(DisasContextBase *dcbase,
CPUState *cpu)
/* Reset the conditional execution bits immediately. This avoids
complications trying to do it at the end of the block. */
if (dc->condexec_mask || dc->condexec_cond) {
- TCGv_i32 tmp = tcg_temp_new_i32();
- tcg_gen_movi_i32(tmp, 0);
- store_cpu_field(tmp, condexec_bits);
+ store_cpu_field_constant(0, condexec_bits);
}
}
--
2.25.1
- [PULL 00/12] target/arm patch queue, Richard Henderson, 2021/11/02
- [PULL 01/12] hw/sd: add nuvoton MMC, Richard Henderson, 2021/11/02
- [PULL 02/12] hw/arm: Add Nuvoton SD module to board, Richard Henderson, 2021/11/02
- [PULL 03/12] hw/arm: Attach MMC to quanta-gbs-bmc, Richard Henderson, 2021/11/02
- [PULL 04/12] tests/qtest/libqos: add SDHCI commands, Richard Henderson, 2021/11/02
- [PULL 05/12] tests/qtest: add qtests for npcm7xx sdhci, Richard Henderson, 2021/11/02
- [PULL 07/12] target/arm: Use tcg_constant_i32() in op_smlad(), Richard Henderson, 2021/11/02
- [PULL 08/12] target/arm: Introduce store_cpu_field_constant() helper, Richard Henderson, 2021/11/02
- [PULL 09/12] target/arm: Use the constant variant of store_cpu_field() when possible,
Richard Henderson <=
- [PULL 10/12] target/arm: Use tcg_constant_i64() in do_sat_addsub_64(), Richard Henderson, 2021/11/02
- [PULL 06/12] target/arm: Advertise MVE to gdb when present, Richard Henderson, 2021/11/02
- [PULL 11/12] target/arm: Use tcg_constant_i32() in gen_rev16(), Richard Henderson, 2021/11/02
- [PULL 12/12] hw/arm/virt: Rename default_bus_bypass_iommu, Richard Henderson, 2021/11/02