[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH v2] hvf: arm: Ignore cache operations on MMIO

From: Peter Maydell
Subject: Re: [PATCH v2] hvf: arm: Ignore cache operations on MMIO
Date: Mon, 1 Nov 2021 17:55:04 +0000

On Tue, 26 Oct 2021 at 17:22, Richard Henderson
<richard.henderson@linaro.org> wrote:
> On 10/26/21 12:12 AM, Alexander Graf wrote:
> > +        if (cm) {
> > +            /* We don't cache MMIO regions */
> > +            advance_pc = true;
> > +            break;
> > +        }
> > +
> >           assert(isv);
> The assert should come first.  If the "iss valid" bit is not set, then 
> nothing else in the
> word is defined.

No, ISV only indicates that ISS[23:14] is valid; ISS[13:0] (including CM)
are valid regardless. (The distinction is that the bits which might or
might not be valid are the ones which encode information about the insn
necessary to possibly emulate it, like the data access size and the
source/destination register; the always-present ones are the ones that
have always been reported for data aborts -- AArch32 DFSR has a CM bit,
for instance.)

-- PMM

reply via email to

[Prev in Thread] Current Thread [Next in Thread]