[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 04/33] hw/riscv: virt: Use machine->ram as the system memory
From: |
Alistair Francis |
Subject: |
[PULL 04/33] hw/riscv: virt: Use machine->ram as the system memory |
Date: |
Fri, 22 Oct 2021 23:37:43 +1000 |
From: Mingwang Li <limingwang@huawei.com>
If default main_mem is used to be registered as the system memory,
other memory cannot be initialized. Therefore, the system memory
should be initialized to the machine->ram, which consists of the
default main_mem and other possible memory required by applications,
such as shared hugepage memory in DPDK.
Also, the mc->defaul_ram_id should be set to the default main_mem,
such as "riscv_virt_board.ram" for the virt machine.
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211016030908.40480-1-limingwang@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/virt.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index ec0cb69b8c..b3b431c847 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -771,7 +771,6 @@ static void virt_machine_init(MachineState *machine)
const MemMapEntry *memmap = virt_memmap;
RISCVVirtState *s = RISCV_VIRT_MACHINE(machine);
MemoryRegion *system_memory = get_system_memory();
- MemoryRegion *main_mem = g_new(MemoryRegion, 1);
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
char *plic_hart_config, *soc_name;
target_ulong start_addr = memmap[VIRT_DRAM].base;
@@ -890,10 +889,8 @@ static void virt_machine_init(MachineState *machine)
}
/* register system main memory (actual RAM) */
- memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram",
- machine->ram_size, &error_fatal);
memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base,
- main_mem);
+ machine->ram);
/* create device tree */
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
@@ -1032,6 +1029,7 @@ static void virt_machine_class_init(ObjectClass *oc, void
*data)
mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
mc->numa_mem_supported = true;
+ mc->default_ram_id = "riscv_virt_board.ram";
machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
--
2.31.1
- [PULL 00/33] riscv-to-apply queue, Alistair Francis, 2021/10/22
- [PULL 01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v, Alistair Francis, 2021/10/22
- [PULL 02/33] target/riscv: line up all of the registers in the info register dump, Alistair Francis, 2021/10/22
- [PULL 03/33] target/riscv: Fix orc.b implementation, Alistair Francis, 2021/10/22
- [PULL 04/33] hw/riscv: virt: Use machine->ram as the system memory,
Alistair Francis <=
- [PULL 05/33] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh, Alistair Francis, 2021/10/22
- [PULL 06/33] target/riscv: Remove some unused macros, Alistair Francis, 2021/10/22
- [PULL 07/33] target/riscv: Organise the CPU properties, Alistair Francis, 2021/10/22
- [PULL 08/33] target/riscv: Move cpu_get_tb_cpu_state out of line, Alistair Francis, 2021/10/22
- [PULL 09/33] target/riscv: Create RISCVMXL enumeration, Alistair Francis, 2021/10/22
- [PULL 10/33] target/riscv: Split misa.mxl and misa.ext, Alistair Francis, 2021/10/22
- [PULL 12/33] target/riscv: Add MXL/SXL/UXL to TB_FLAGS, Alistair Francis, 2021/10/22
- [PULL 11/33] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl, Alistair Francis, 2021/10/22
- [PULL 13/33] target/riscv: Use REQUIRE_64BIT in amo_check64, Alistair Francis, 2021/10/22
- [PULL 14/33] target/riscv: Properly check SEW in amo_op, Alistair Francis, 2021/10/22