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[PATCH 33/33] target/ppc: Implement lxvkq instruction
From: |
matheus . ferst |
Subject: |
[PATCH 33/33] target/ppc: Implement lxvkq instruction |
Date: |
Thu, 21 Oct 2021 16:45:47 -0300 |
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn32.decode | 7 +++++
target/ppc/translate/vsx-impl.c.inc | 44 +++++++++++++++++++++++++++++
2 files changed, 51 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index fd73946122..e135b8aba4 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -100,6 +100,9 @@
&X_imm8 xt imm:uint8_t
@X_imm8 ...... ..... .. imm:8 .......... . &X_imm8
xt=%x_xt
+&X_uim5 xt uim:uint8_t
+@X_uim5 ...... ..... ..... uim:5 .......... . &X_uim5
xt=%x_xt
+
&X_tb_sp_rc rt rb sp rc:bool
@X_tb_sp_rc ...... rt:5 sp:2 ... rb:5 .......... rc:1 &X_tb_sp_rc
@@ -420,3 +423,7 @@ STXVPX 011111 ..... ..... ..... 0111001101 -
@X_TSXP
XXSPLTIB 111100 ..... 00 ........ 0101101000 . @X_imm8
XXSPLTW 111100 ..... ---.. ..... 010100100 . . @XX2
+
+## VSX Vector Load Special Value Instruction
+
+LXVKQ 111100 ..... 11111 ..... 0101101000 . @X_uim5
diff --git a/target/ppc/translate/vsx-impl.c.inc
b/target/ppc/translate/vsx-impl.c.inc
index 4619d7f238..badf70cb01 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1552,6 +1552,50 @@ static bool trans_XXSPLTI32DX(DisasContext *ctx,
arg_8RR_D_IX *a)
return true;
}
+static bool trans_LXVKQ(DisasContext *ctx, arg_X_uim5 *a)
+{
+ static const uint32_t valid_values = 0b00000001111111110000001111111110;
+ static const uint64_t values[32] = {
+ 0, /* Unspecified */
+ 0x3FFF000000000000llu, /* QP +1.0 */
+ 0x4000000000000000llu, /* QP +2.0 */
+ 0x4000800000000000llu, /* QP +3.0 */
+ 0x4001000000000000llu, /* QP +4.0 */
+ 0x4001400000000000llu, /* QP +5.0 */
+ 0x4001800000000000llu, /* QP +6.0 */
+ 0x4001C00000000000llu, /* QP +7.0 */
+ 0x7FFF000000000000llu, /* QP +Inf */
+ 0x7FFF800000000000llu, /* QP dQNaN */
+ 0, /* Unspecified */
+ 0, /* Unspecified */
+ 0, /* Unspecified */
+ 0, /* Unspecified */
+ 0, /* Unspecified */
+ 0, /* Unspecified */
+ 0x8000000000000000llu, /* QP -0.0 */
+ 0xBFFF000000000000llu, /* QP -1.0 */
+ 0xC000000000000000llu, /* QP -2.0 */
+ 0xC000800000000000llu, /* QP -3.0 */
+ 0xC001000000000000llu, /* QP -4.0 */
+ 0xC001400000000000llu, /* QP -5.0 */
+ 0xC001800000000000llu, /* QP -6.0 */
+ 0xC001C00000000000llu, /* QP -7.0 */
+ 0xFFFF000000000000llu, /* QP -Inf */
+ };
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VSX(ctx);
+
+ if (!(valid_values & (1 << a->uim))) {
+ gen_invalid(ctx);
+ } else {
+ set_cpu_vsrl(a->xt, tcg_constant_i64(0x0));
+ set_cpu_vsrh(a->xt, tcg_constant_i64(values[a->uim]));
+ }
+
+ return true;
+}
+
static void gen_xxsldwi(DisasContext *ctx)
{
TCGv_i64 xth, xtl;
--
2.25.1
- [PATCH 28/33] target/ppc: moved XXSPLTIB to using decodetree, (continued)
- [PATCH 28/33] target/ppc: moved XXSPLTIB to using decodetree, matheus . ferst, 2021/10/21
- [PATCH 29/33] target/ppc: implemented XXSPLTI32DX, matheus . ferst, 2021/10/21
- [PATCH 30/33] target/ppc: Implemented XXSPLTIW using decodetree, matheus . ferst, 2021/10/21
- [PATCH 31/33] target/ppc: implemented XXSPLTIDP instruction, matheus . ferst, 2021/10/21
- [PATCH 32/33] target/ppc: Implement xxblendvb/xxblendvh/xxblendvw/xxblendvd instructions, matheus . ferst, 2021/10/21
- [PATCH 33/33] target/ppc: Implement lxvkq instruction,
matheus . ferst <=
- [PATCH 18/33] target/ppc: Move vinsertb/vinserth/vinsertw/vinsertd to decodetree, matheus . ferst, 2021/10/21
- Re: [PATCH 00/33] PowerISA v3.1 instruction batch, Richard Henderson, 2021/10/21