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Re: [PATCH v3 14/14] target/riscv: Compute mstatus.sd on demand
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v3 14/14] target/riscv: Compute mstatus.sd on demand |
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Date: |
Mon, 18 Oct 2021 15:38:12 +1000 |
On Mon, Oct 18, 2021 at 3:31 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 10/17/21 9:52 PM, Alistair Francis wrote:
> > On Sun, Oct 17, 2021 at 3:32 AM Richard Henderson
> > <richard.henderson@linaro.org> wrote:
> >>
> >> The position of this read-only field is dependent on the
> >> current cpu width. Rather than having to compute that
> >> difference in many places, compute it only on read.
> >>
> >> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> >
> > This means that the value reported by riscv_cpu_dump_state() and GDB
> > will both be incorrect though?
>
> Yep. Missed those; should have added another accessor.
Do we get much of an advantage from this though? To me it seems
confusing that the mstatus register doesn't actually contain the
latest value (for example when debugging QEMU and adding my own
printf's).
>
> Also, for the record, it changes the vmstate, but since a previous patch in
> the series
> bumped the version number for the split on misa, we can call all of a piece
> and ok.
Works for me :)
Alistair
>
>
> r~
- Re: [PATCH v3 05/14] target/riscv: Add MXL/SXL/UXL to TB_FLAGS, (continued)
- [PATCH v3 08/14] target/riscv: Replace is_32bit with get_xl/get_xlen, Richard Henderson, 2021/10/16
- [PATCH v3 11/14] target/riscv: Adjust trans_rev8_32 for riscv64, Richard Henderson, 2021/10/16
- [PATCH v3 10/14] target/riscv: Use gen_arith_per_ol for RVM, Richard Henderson, 2021/10/16
- [PATCH v3 09/14] target/riscv: Replace DisasContext.w with DisasContext.ol, Richard Henderson, 2021/10/16
- [PATCH v3 06/14] target/riscv: Use REQUIRE_64BIT in amo_check64, Richard Henderson, 2021/10/16
- [PATCH v3 14/14] target/riscv: Compute mstatus.sd on demand, Richard Henderson, 2021/10/16
[PATCH v3 12/14] target/riscv: Use gen_unary_per_ol for RVB, Richard Henderson, 2021/10/16
[PATCH v3 13/14] target/riscv: Use gen_shift*_per_ol for RVB, RVI, Richard Henderson, 2021/10/16