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[PATCH v8 78/78] target/riscv: rvv-1.0: update opivv_vadc_check() commen
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From: |
frank . chang |
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Subject: |
[PATCH v8 78/78] target/riscv: rvv-1.0: update opivv_vadc_check() comment |
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Date: |
Fri, 15 Oct 2021 15:46:26 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions is
moved to Section 11.4 in RVV v1.0 spec. Update the comment, no
functional changes.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index b78c13f0be7..de2e2e506fe 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1613,7 +1613,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
/*
* For vadc and vsbc, an illegal instruction exception is raised if the
- * destination vector register is v0 and LMUL > 1. (Section 12.4)
+ * destination vector register is v0 and LMUL > 1. (Section 11.4)
*/
static bool opivv_vadc_check(DisasContext *s, arg_rmrr *a)
{
--
2.25.1
- [PATCH v8 70/78] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction, (continued)
- [PATCH v8 70/78] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction, frank . chang, 2021/10/15
- [PATCH v8 71/78] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction, frank . chang, 2021/10/15
- [PATCH v8 72/78] target/riscv: set mstatus.SD bit when writing fp CSRs, frank . chang, 2021/10/15
- [PATCH v8 73/78] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11, frank . chang, 2021/10/15
- [PATCH v8 74/78] target/riscv: rvv-1.0: add vsetivli instruction, frank . chang, 2021/10/15
- [PATCH v8 75/78] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us(), frank . chang, 2021/10/15
- [PATCH v8 76/78] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns, frank . chang, 2021/10/15
- [PATCH v8 78/78] target/riscv: rvv-1.0: update opivv_vadc_check() comment,
frank . chang <=
- [PATCH v8 77/78] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm, frank . chang, 2021/10/15
- Re: [PATCH v8 00/78] support vector extension v1.0, Frank Chang, 2021/10/15
- Re: [PATCH v8 00/78] support vector extension v1.0, Alistair Francis, 2021/10/18
- Re: [PATCH v8 00/78] support vector extension v1.0, LIU Zhiwei, 2021/10/18