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[PATCH v3 39/41] target/sparc: Make sparc_cpu_tlb_fill sysemu only
From: |
Richard Henderson |
Subject: |
[PATCH v3 39/41] target/sparc: Make sparc_cpu_tlb_fill sysemu only |
Date: |
Fri, 1 Oct 2021 13:11:49 -0400 |
The fallback code in raise_sigsegv is sufficient for sparc.
This makes all of the code in mmu_helper.c sysemu only, so remove
the ifdefs and move the file to sparc_softmmu_ss. Remove the code
from cpu_loop that handled TT_DFAULT and TT_TFAULT.
Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/sparc/cpu_loop.c | 25 -------------------------
target/sparc/cpu.c | 2 +-
target/sparc/mmu_helper.c | 25 -------------------------
target/sparc/meson.build | 2 +-
4 files changed, 2 insertions(+), 52 deletions(-)
diff --git a/linux-user/sparc/cpu_loop.c b/linux-user/sparc/cpu_loop.c
index ad29b4eb6a..0ba65e431c 100644
--- a/linux-user/sparc/cpu_loop.c
+++ b/linux-user/sparc/cpu_loop.c
@@ -219,17 +219,6 @@ void cpu_loop (CPUSPARCState *env)
case TT_WIN_UNF: /* window underflow */
restore_window(env);
break;
- case TT_TFAULT:
- case TT_DFAULT:
- {
- info.si_signo = TARGET_SIGSEGV;
- info.si_errno = 0;
- /* XXX: check env->error_code */
- info.si_code = TARGET_SEGV_MAPERR;
- info._sifields._sigfault._addr = env->mmuregs[4];
- queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
- }
- break;
#else
case TT_SPILL: /* window overflow */
save_window(env);
@@ -237,20 +226,6 @@ void cpu_loop (CPUSPARCState *env)
case TT_FILL: /* window underflow */
restore_window(env);
break;
- case TT_TFAULT:
- case TT_DFAULT:
- {
- info.si_signo = TARGET_SIGSEGV;
- info.si_errno = 0;
- /* XXX: check env->error_code */
- info.si_code = TARGET_SEGV_MAPERR;
- if (trapnr == TT_DFAULT)
- info._sifields._sigfault._addr = env->dmmu.mmuregs[4];
- else
- info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
- queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
- }
- break;
#ifndef TARGET_ABI32
case 0x16e:
flush_windows(env);
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 21dd27796d..55268ed2a1 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -865,9 +865,9 @@ static const struct SysemuCPUOps sparc_sysemu_ops = {
static const struct TCGCPUOps sparc_tcg_ops = {
.initialize = sparc_tcg_init,
.synchronize_from_tb = sparc_cpu_synchronize_from_tb,
- .tlb_fill = sparc_cpu_tlb_fill,
#ifndef CONFIG_USER_ONLY
+ .tlb_fill = sparc_cpu_tlb_fill,
.cpu_exec_interrupt = sparc_cpu_exec_interrupt,
.do_interrupt = sparc_cpu_do_interrupt,
.do_transaction_failed = sparc_cpu_do_transaction_failed,
diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c
index a44473a1c7..2ad47391d0 100644
--- a/target/sparc/mmu_helper.c
+++ b/target/sparc/mmu_helper.c
@@ -25,30 +25,6 @@
/* Sparc MMU emulation */
-#if defined(CONFIG_USER_ONLY)
-
-bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
- MMUAccessType access_type, int mmu_idx,
- bool probe, uintptr_t retaddr)
-{
- SPARCCPU *cpu = SPARC_CPU(cs);
- CPUSPARCState *env = &cpu->env;
-
- if (access_type == MMU_INST_FETCH) {
- cs->exception_index = TT_TFAULT;
- } else {
- cs->exception_index = TT_DFAULT;
-#ifdef TARGET_SPARC64
- env->dmmu.mmuregs[4] = address;
-#else
- env->mmuregs[4] = address;
-#endif
- }
- cpu_loop_exit_restore(cs, retaddr);
-}
-
-#else
-
#ifndef TARGET_SPARC64
/*
* Sparc V8 Reference MMU (SRMMU)
@@ -926,4 +902,3 @@ hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vaddr
addr)
}
return phys_addr;
}
-#endif
diff --git a/target/sparc/meson.build b/target/sparc/meson.build
index a3638b9503..a801802ee2 100644
--- a/target/sparc/meson.build
+++ b/target/sparc/meson.build
@@ -6,7 +6,6 @@ sparc_ss.add(files(
'gdbstub.c',
'helper.c',
'ldst_helper.c',
- 'mmu_helper.c',
'translate.c',
'win_helper.c',
))
@@ -16,6 +15,7 @@ sparc_ss.add(when: 'TARGET_SPARC64', if_true:
files('int64_helper.c', 'vis_helpe
sparc_softmmu_ss = ss.source_set()
sparc_softmmu_ss.add(files(
'machine.c',
+ 'mmu_helper.c',
'monitor.c',
))
--
2.25.1
- [PATCH v3 17/41] linux-user/host/riscv: Improve host_signal_write, (continued)
- [PATCH v3 17/41] linux-user/host/riscv: Improve host_signal_write, Richard Henderson, 2021/10/01
- [PATCH v3 19/41] hw/core: Add TCGCPUOps.record_sigsegv, Richard Henderson, 2021/10/01
- [PATCH v3 32/41] linux-user/openrisc: Adjust signal for EXCP_RANGE, EXCP_FPE, Richard Henderson, 2021/10/01
- [PATCH v3 30/41] target/mips: Make mips_cpu_tlb_fill sysemu only, Richard Henderson, 2021/10/01
- [PATCH v3 31/41] target/nios2: Implement nios2_cpu_record_sigsegv, Richard Henderson, 2021/10/01
- [PATCH v3 35/41] target/riscv: Make riscv_cpu_tlb_fill sysemu only, Richard Henderson, 2021/10/01
- [PATCH v3 37/41] target/s390x: Implement s390_cpu_record_sigsegv, Richard Henderson, 2021/10/01
- [PATCH v3 39/41] target/sparc: Make sparc_cpu_tlb_fill sysemu only,
Richard Henderson <=
- [PATCH v3 26/41] target/hppa: Make hppa_cpu_tlb_fill sysemu only, Richard Henderson, 2021/10/01
- [PATCH v3 21/41] target/alpha: Make alpha_cpu_tlb_fill sysemu only, Richard Henderson, 2021/10/01
- [PATCH v3 22/41] target/arm: Use cpu_loop_exit_segv for mte tag lookup, Richard Henderson, 2021/10/01
- [PATCH v3 23/41] target/arm: Implement arm_cpu_record_sigsegv, Richard Henderson, 2021/10/01
- [PATCH v3 29/41] target/microblaze: Make mb_cpu_tlb_fill sysemu only, Richard Henderson, 2021/10/01
- [PATCH v3 33/41] target/openrisc: Make openrisc_cpu_tlb_fill sysemu only, Richard Henderson, 2021/10/01