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Re: [PATCH 04/30] tcg/loongarch: Add generated instruction opcodes and e
From: |
Philippe Mathieu-Daudé |
Subject: |
Re: [PATCH 04/30] tcg/loongarch: Add generated instruction opcodes and encoding helpers |
Date: |
Tue, 21 Sep 2021 11:58:50 +0200 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.1.0 |
On 9/20/21 10:04, WANG Xuerui wrote:
Signed-off-by: WANG Xuerui <git@xen0n.name>
---
tcg/loongarch/tcg-insn-defs.c.inc | 1080 +++++++++++++++++++++++++++++
1 file changed, 1080 insertions(+)
create mode 100644 tcg/loongarch/tcg-insn-defs.c.inc
+static int32_t encode_dj_slots(LoongArchInsn opc, uint32_t d, uint32_t j)
+{
Can we move the range check to the callee and avoid masking the values
in the caller?
tcg_debug_assert(d < 0x20);
tcg_debug_assert(j < 0x20);
+ return opc | d | j << 5;
+}
+
+static int32_t encode_djk_slots(LoongArchInsn opc, uint32_t d, uint32_t j,
+ uint32_t k) __attribute__((unused));
+
+static int32_t encode_djk_slots(LoongArchInsn opc, uint32_t d, uint32_t j,
+ uint32_t k)
+{
tcg_debug_assert(d < 0x20);
tcg_debug_assert(j < 0x20);
+ return opc | d | j << 5 | k << 10;
+}
+
+static int32_t encode_djkm_slots(LoongArchInsn opc, uint32_t d, uint32_t j,
+ uint32_t k, uint32_t m)
+ __attribute__((unused));
+
+static int32_t encode_djkm_slots(LoongArchInsn opc, uint32_t d, uint32_t j,
+ uint32_t k, uint32_t m)
+{
+ return opc | d | j << 5 | k << 10 | m << 16;
+}
+
+static int32_t encode_dk_slots(LoongArchInsn opc, uint32_t d, uint32_t k)
+ __attribute__((unused));
+
+static int32_t encode_dk_slots(LoongArchInsn opc, uint32_t d, uint32_t k)
+{
+ return opc | d | k << 10;
+}
+
+static int32_t encode_dj_insn(LoongArchInsn opc, TCGReg d, TCGReg j)
+ __attribute__((unused));
+
+static int32_t encode_dj_insn(LoongArchInsn opc, TCGReg d, TCGReg j)
+{
+ d &= 0x1f;
+ j &= 0x1f;
+ return encode_dj_slots(opc, d, j);
+}
+
+static int32_t encode_djk_insn(LoongArchInsn opc, TCGReg d, TCGReg j, TCGReg k)
+ __attribute__((unused));
+
+static int32_t encode_djk_insn(LoongArchInsn opc, TCGReg d, TCGReg j, TCGReg k)
+{
+ d &= 0x1f;
+ j &= 0x1f;
^ moved to encode_djk_slots()
+ k &= 0x1f;
tcg_debug_assert(k < 0x20);
+ return encode_djk_slots(opc, d, j, k);
+}
+
+static int32_t encode_djsk12_insn(LoongArchInsn opc, TCGReg d, TCGReg j,
+ int32_t sk12) __attribute__((unused));
+
+static int32_t encode_djsk12_insn(LoongArchInsn opc, TCGReg d, TCGReg j,
+ int32_t sk12)
+{
+ d &= 0x1f;
+ j &= 0x1f;
^ moved to encode_djk_slots()
+ sk12 &= 0xfff;
tcg_debug_assert(sk12 < 0x1000);
+ return encode_djk_slots(opc, d, j, sk12);
+}
+
+static int32_t encode_djsk16_insn(LoongArchInsn opc, TCGReg d, TCGReg j,
+ int32_t sk16) __attribute__((unused));
+
+static int32_t encode_djsk16_insn(LoongArchInsn opc, TCGReg d, TCGReg j,
+ int32_t sk16)
+{
+ d &= 0x1f;
+ j &= 0x1f;
^ moved to encode_djk_slots()
+ sk16 &= 0xffff;
tcg_debug_assert(sk16 < 0x10000);
+ return encode_djk_slots(opc, d, j, sk16);
+}
etc...
- Re: [PATCH 21/30] tcg/loongarch: Implement tcg_out_call, (continued)
- [PATCH 12/30] tcg/loongarch: Implement not/and/or/xor/nor/andc/orc ops, WANG Xuerui, 2021/09/20
- [PATCH 14/30] tcg/loongarch: Implement bswap32_i32/bswap64_i64, WANG Xuerui, 2021/09/20
- [PATCH 04/30] tcg/loongarch: Add generated instruction opcodes and encoding helpers, WANG Xuerui, 2021/09/20
- [PATCH 19/30] tcg/loongarch: Implement br/brcond ops, WANG Xuerui, 2021/09/20
- [PATCH 17/30] tcg/loongarch: Implement neg/add/sub ops, WANG Xuerui, 2021/09/20
- [PATCH 11/30] tcg/loongarch: Implement sign-/zero-extension ops, WANG Xuerui, 2021/09/20
- [PATCH 20/30] tcg/loongarch: Implement setcond ops, WANG Xuerui, 2021/09/20
- [PATCH 15/30] tcg/loongarch: Implement clz/ctz ops, WANG Xuerui, 2021/09/20