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[PATCH 17/30] tcg/loongarch: Implement neg/add/sub ops
From: |
WANG Xuerui |
Subject: |
[PATCH 17/30] tcg/loongarch: Implement neg/add/sub ops |
Date: |
Mon, 20 Sep 2021 16:04:38 +0800 |
Signed-off-by: WANG Xuerui <git@xen0n.name>
---
tcg/loongarch/tcg-target-con-set.h | 2 ++
tcg/loongarch/tcg-target.c.inc | 47 ++++++++++++++++++++++++++++++
2 files changed, 49 insertions(+)
diff --git a/tcg/loongarch/tcg-target-con-set.h
b/tcg/loongarch/tcg-target-con-set.h
index 8630d1ee6e..58b5c487e2 100644
--- a/tcg/loongarch/tcg-target-con-set.h
+++ b/tcg/loongarch/tcg-target-con-set.h
@@ -18,6 +18,8 @@ C_O0_I1(r)
C_O1_I1(r, r)
C_O1_I2(r, r, r)
C_O1_I2(r, r, ri)
+C_O1_I2(r, r, rI)
C_O1_I2(r, r, rU)
C_O1_I2(r, r, rZ)
C_O1_I2(r, 0, rZ)
+C_O1_I2(r, rZ, rN)
diff --git a/tcg/loongarch/tcg-target.c.inc b/tcg/loongarch/tcg-target.c.inc
index acbd0e65ef..e5518c0102 100644
--- a/tcg/loongarch/tcg-target.c.inc
+++ b/tcg/loongarch/tcg-target.c.inc
@@ -592,6 +592,43 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
break;
+ case INDEX_op_neg_i32:
+ tcg_out_opc_sub_w(s, a0, TCG_REG_ZERO, a1);
+ break;
+ case INDEX_op_neg_i64:
+ tcg_out_opc_sub_d(s, a0, TCG_REG_ZERO, a1);
+ break;
+
+ case INDEX_op_add_i32:
+ if (c2) {
+ tcg_out_opc_addi_w(s, a0, a1, a2);
+ } else {
+ tcg_out_opc_add_w(s, a0, a1, a2);
+ }
+ break;
+ case INDEX_op_add_i64:
+ if (c2) {
+ tcg_out_opc_addi_d(s, a0, a1, a2);
+ } else {
+ tcg_out_opc_add_d(s, a0, a1, a2);
+ }
+ break;
+
+ case INDEX_op_sub_i32:
+ if (c2) {
+ tcg_out_opc_addi_w(s, a0, a1, -a2);
+ } else {
+ tcg_out_opc_sub_w(s, a0, a1, a2);
+ }
+ break;
+ case INDEX_op_sub_i64:
+ if (c2) {
+ tcg_out_opc_addi_d(s, a0, a1, -a2);
+ } else {
+ tcg_out_opc_sub_d(s, a0, a1, a2);
+ }
+ break;
+
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
default:
@@ -625,6 +662,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_extract_i64:
case INDEX_op_bswap32_i32:
case INDEX_op_bswap64_i64:
+ case INDEX_op_neg_i32:
+ case INDEX_op_neg_i64:
return C_O1_I1(r, r);
case INDEX_op_nor_i32:
@@ -648,6 +687,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode
op)
case INDEX_op_rotr_i64:
return C_O1_I2(r, r, ri);
+ case INDEX_op_add_i32:
+ case INDEX_op_add_i64:
+ return C_O1_I2(r, r, rI);
+
case INDEX_op_and_i32:
case INDEX_op_or_i32:
case INDEX_op_xor_i32:
@@ -668,6 +711,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode
op)
/* Must deposit into the same register as input */
return C_O1_I2(r, 0, rZ);
+ case INDEX_op_sub_i32:
+ case INDEX_op_sub_i64:
+ return C_O1_I2(r, rZ, rN);
+
default:
g_assert_not_reached();
}
--
2.33.0
- [PATCH 21/30] tcg/loongarch: Implement tcg_out_call, (continued)
- [PATCH 21/30] tcg/loongarch: Implement tcg_out_call, WANG Xuerui, 2021/09/20
- [PATCH 12/30] tcg/loongarch: Implement not/and/or/xor/nor/andc/orc ops, WANG Xuerui, 2021/09/20
- [PATCH 14/30] tcg/loongarch: Implement bswap32_i32/bswap64_i64, WANG Xuerui, 2021/09/20
- [PATCH 04/30] tcg/loongarch: Add generated instruction opcodes and encoding helpers, WANG Xuerui, 2021/09/20
- [PATCH 19/30] tcg/loongarch: Implement br/brcond ops, WANG Xuerui, 2021/09/20
- [PATCH 17/30] tcg/loongarch: Implement neg/add/sub ops,
WANG Xuerui <=
- [PATCH 11/30] tcg/loongarch: Implement sign-/zero-extension ops, WANG Xuerui, 2021/09/20
- [PATCH 20/30] tcg/loongarch: Implement setcond ops, WANG Xuerui, 2021/09/20
- [PATCH 15/30] tcg/loongarch: Implement clz/ctz ops, WANG Xuerui, 2021/09/20
- [PATCH 18/30] tcg/loongarch: Implement mul/mulsh/muluh/div/divu/rem/remu ops, WANG Xuerui, 2021/09/20
- [PATCH 08/30] tcg/loongarch: Implement the memory barrier op, WANG Xuerui, 2021/09/20