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[PATCH v2 34/41] target/ppc: Implement ppc_cpu_record_sigsegv
From: |
Richard Henderson |
Subject: |
[PATCH v2 34/41] target/ppc: Implement ppc_cpu_record_sigsegv |
Date: |
Sat, 18 Sep 2021 11:45:20 -0700 |
Record DAR, DSISR, and exception_index. That last means
that we must exit to cpu_loop ourselves, instead of letting
exception_index being overwritten.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/cpu.h | 3 ---
target/ppc/internal.h | 9 +++++++++
target/ppc/cpu_init.c | 6 ++++--
target/ppc/user_only_helper.c | 15 +++++++++++----
4 files changed, 24 insertions(+), 9 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 01d3773bc7..60d1117845 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1278,9 +1278,6 @@ extern const VMStateDescription vmstate_ppc_cpu;
/*****************************************************************************/
void ppc_translate_init(void);
-bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
- MMUAccessType access_type, int mmu_idx,
- bool probe, uintptr_t retaddr);
#if !defined(CONFIG_USER_ONLY)
void ppc_store_sdr1(CPUPPCState *env, target_ulong value);
diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index b71406fa46..f3e5aa8fbc 100644
--- a/target/ppc/internal.h
+++ b/target/ppc/internal.h
@@ -283,5 +283,14 @@ static inline void pte_invalidate(target_ulong *pte0)
#define PTE_PTEM_MASK 0x7FFFFFBF
#define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B)
+#ifdef CONFIG_USER_ONLY
+void ppc_cpu_record_sigsegv(CPUState *cs, vaddr addr,
+ MMUAccessType access_type,
+ bool maperr, uintptr_t ra);
+#else
+bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+ MMUAccessType access_type, int mmu_idx,
+ bool probe, uintptr_t retaddr);
+#endif
#endif /* PPC_INTERNAL_H */
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 5c134adeea..d56fde1215 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -9028,10 +9028,12 @@ static const struct SysemuCPUOps ppc_sysemu_ops = {
static const struct TCGCPUOps ppc_tcg_ops = {
.initialize = ppc_translate_init,
- .tlb_fill = ppc_cpu_tlb_fill,
-#ifndef CONFIG_USER_ONLY
+#ifdef CONFIG_USER_ONLY
+ .record_sigsegv = ppc_cpu_record_sigsegv,
+#else
.has_work = ppc_cpu_has_work,
+ .tlb_fill = ppc_cpu_tlb_fill,
.cpu_exec_interrupt = ppc_cpu_exec_interrupt,
.do_interrupt = ppc_cpu_do_interrupt,
.cpu_exec_enter = ppc_cpu_exec_enter,
diff --git a/target/ppc/user_only_helper.c b/target/ppc/user_only_helper.c
index aa3f867596..7ff76f7a06 100644
--- a/target/ppc/user_only_helper.c
+++ b/target/ppc/user_only_helper.c
@@ -21,16 +21,23 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/exec-all.h"
+#include "internal.h"
-
-bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
- MMUAccessType access_type, int mmu_idx,
- bool probe, uintptr_t retaddr)
+void ppc_cpu_record_sigsegv(CPUState *cs, vaddr address,
+ MMUAccessType access_type,
+ bool maperr, uintptr_t retaddr)
{
PowerPCCPU *cpu = POWERPC_CPU(cs);
CPUPPCState *env = &cpu->env;
int exception, error_code;
+ /*
+ * Both DSISR and the "trap number" (exception vector offset,
+ * looked up from exception_index) are present in the linux-user
+ * signal frame.
+ * FIXME: we don't actually populate the trap number properly.
+ * It would be easiest to fill in an env->trap value now.
+ */
if (access_type == MMU_INST_FETCH) {
exception = POWERPC_EXCP_ISI;
error_code = 0x40000000;
--
2.25.1
- [PATCH v2 36/41] target/s390x: Use probe_access_flags in s390_probe_access, (continued)
- [PATCH v2 36/41] target/s390x: Use probe_access_flags in s390_probe_access, Richard Henderson, 2021/09/18
- [PATCH v2 39/41] target/sparc: Make sparc_cpu_tlb_fill sysemu only, Richard Henderson, 2021/09/18
- [PATCH v2 30/41] target/mips: Make mips_cpu_tlb_fill sysemu only, Richard Henderson, 2021/09/18
- [PATCH v2 28/41] target/m68k: Make m68k_cpu_tlb_fill sysemu only, Richard Henderson, 2021/09/18
- [PATCH v2 37/41] target/s390x: Implement s390_cpu_record_sigsegv, Richard Henderson, 2021/09/18
- [PATCH v2 38/41] target/sh4: Make sh4_cpu_tlb_fill sysemu only, Richard Henderson, 2021/09/18
- [PATCH v2 32/41] linux-user/openrisc: Adjust signal for EXCP_RANGE, EXCP_FPE, Richard Henderson, 2021/09/18
- [PATCH v2 31/41] target/nios2: Make nios2_cpu_tlb_fill sysemu only, Richard Henderson, 2021/09/18
- [PATCH v2 25/41] target/hexagon: Remove hexagon_cpu_tlb_fill, Richard Henderson, 2021/09/18
- [PATCH v2 34/41] target/ppc: Implement ppc_cpu_record_sigsegv,
Richard Henderson <=
- [PATCH v2 33/41] target/openrisc: Make openrisc_cpu_tlb_fill sysemu only, Richard Henderson, 2021/09/18
- [PATCH v2 40/41] target/xtensa: Make xtensa_cpu_tlb_fill sysemu only, Richard Henderson, 2021/09/18
- [PATCH v2 41/41] accel/tcg: Restrict TCGCPUOps::tlb_fill() to sysemu, Richard Henderson, 2021/09/18
- Re: [PATCH v2 00/41] linux-user: Streamline handling of SIGSEGV, Philippe Mathieu-Daudé, 2021/09/19