[RFC 10/10] target/riscv: rvb: add funnel shfit instructions

[Eric Tang]

    Add funnel shfit instructions except fsri/fsriw for opcode ecoding
    reason.

Signed-off-by: Eric Tang <tangxingxin1008@gmail.com>

diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
index e936444c12..08a2fbb376 100644
--- a/target/riscv/bitmanip_helper.c
+++ b/target/riscv/bitmanip_helper.c
@@ -124,6 +124,43 @@ target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong 
rs2)
     return do_clmulr(rs1, rs2, TARGET_LONG_BITS);
 }
 
+static target_ulong do_fsl(target_ulong rs1,
+                           target_ulong rs2,
+                           target_ulong rs3,
+                           int bits)
+{
+    int shamt = rs2 & ((2 * bits) - 1);
+    target_ulong a = rs1, b = rs3;
+
+    if (shamt >= bits) {
+        shamt -= bits;
+        a = rs3;
+        b = rs1;
+    }
+
+    return shamt ? (a << shamt) | (b >> (bits - shamt)) : a;
+}
+
+target_ulong HELPER(fsl)(target_ulong rs1, target_ulong rs2, target_ulong rs3)
+{
+    return do_fsl(rs1, rs2, rs3, TARGET_LONG_BITS);
+}
+
+target_ulong HELPER(fsr)(target_ulong rs1, target_ulong rs2, target_ulong rs3)
+{
+    return do_fsl(rs1, -rs2, rs3, TARGET_LONG_BITS);
+}
+
+target_ulong HELPER(fslw)(target_ulong rs1, target_ulong rs2, target_ulong rs3)
+{
+    return do_fsl(rs1, rs2, rs3, 32);
+}
+
+target_ulong HELPER(fsrw)(target_ulong rs1, target_ulong rs2, target_ulong rs3)
+{
+    return do_fsl(rs1, -rs2, rs3, 32);
+}
+
 static target_ulong shuffle_stage(target_ulong src,
                                   uint64_t maskl,
                                   uint64_t maskr,
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 8c8fb71bb4..619f635b6d 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -87,6 +87,10 @@ DEF_HELPER_FLAGS_1(crc32c_d, TCG_CALL_NO_RWG_SE, tl, tl)
 DEF_HELPER_FLAGS_2(bmatxor, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(bmator, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_1(bmatflip, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_3(fsl, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
+DEF_HELPER_FLAGS_3(fsr, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
+DEF_HELPER_FLAGS_3(fslw, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
+DEF_HELPER_FLAGS_3(fsrw, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
 
 /* Special functions */
 DEF_HELPER_2(csrr, tl, env, int)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 73f956486b..65e574709a 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -713,6 +713,8 @@ xperm_h    0010100 .......... 110 ..... 0110011 @r
 bfp        0100100 .......... 111 ..... 0110011 @r
 cmix       .....11 .......... 001 ..... 0110011 @r4
 cmov       .....11 .......... 101 ..... 0110011 @r4
+fsl        .....10 .......... 001 ..... 0110011 @r4
+fsr        .....10 .......... 101 ..... 0110011 @r4
 
 bseti      00101. ........... 001 ..... 0010011 @sh
 bclri      01001. ........... 001 ..... 0010011 @sh
@@ -754,6 +756,8 @@ xperm_w    0010100 .......... 000 ..... 0110011 @r
 bfpw       0100100 .......... 111 ..... 0111011 @r
 bmator     0000100 .......... 011 ..... 0110011 @r
 bmatxor    0100100 .......... 011 ..... 0110011 @r
+fslw       .....10 .......... 001 ..... 0111011 @r4
+fsrw       .....10 .......... 101 ..... 0111011 @r4
 
 bsetiw     0010100 .......... 001 ..... 0011011 @sh5
 bclriw     0100100 .......... 001 ..... 0011011 @sh5
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc 
b/target/riscv/insn_trans/trans_rvb.c.inc
index 4523a5cd4c..5315baa185 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -428,6 +428,18 @@ static bool trans_cmov(DisasContext *ctx, arg_cmov *a)
     return gen_quat(ctx, a, EXT_NONE, gen_cmov);
 }
 
+static bool trans_fsl(DisasContext *ctx, arg_fsl *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_quat(ctx, a, EXT_NONE, gen_helper_fsl);
+}
+
+static bool trans_fsr(DisasContext *ctx, arg_fsr *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_quat(ctx, a, EXT_NONE, gen_helper_fsr);
+}
+
 #define GEN_SHADD(SHAMT)                                       \
 static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \
 {                                                              \
@@ -827,3 +839,19 @@ static bool trans_bmator(DisasContext *ctx, arg_bmator *a)
     REQUIRE_EXT(ctx, RVB);
     return gen_arith(ctx, a, EXT_NONE, gen_helper_bmator);
 }
+
+static bool trans_fslw(DisasContext *ctx, arg_fslw *a)
+{
+    REQUIRE_64BIT(ctx);
+    REQUIRE_EXT(ctx, RVB);
+    ctx->w = true;
+    return gen_quat(ctx, a, EXT_ZERO, gen_helper_fslw);
+}
+
+static bool trans_fsrw(DisasContext *ctx, arg_fsrw *a)
+{
+    REQUIRE_64BIT(ctx);
+    REQUIRE_EXT(ctx, RVB);
+    ctx->w = true;
+    return gen_quat(ctx, a, EXT_ZERO, gen_helper_fsrw);
+}
-- 
2.17.1