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[PULL 16/21] hw/dma: sifive_pdma: allow non-multiple transaction size tr
From: |
Alistair Francis |
Subject: |
[PULL 16/21] hw/dma: sifive_pdma: allow non-multiple transaction size transactions |
Date: |
Fri, 17 Sep 2021 07:48:59 +1000 |
From: Green Wan <green.wan@sifive.com>
Real PDMA is able to deal with non-multiple transaction size transactions.
The following result is PDMA tested in U-Boot on Unmatched board:
=> mw.l 0x3000000 0x0 <= Disclaim channel 0
=> mw.l 0x3000000 0x1 <= Claim channel 0
=> mw.l 0x3000004 0x11000000 <= wsize = rsize = 1 (2^1 = 2 bytes)
=> mw.q 0x3000008 0x3 <= NextBytes = 3
=> mw.q 0x3000010 0x84000000 <= NextDestination = 0x84000000
=> mw.q 0x3000018 0x84001000 <= NextSource = 0x84001000
=> mw.l 0x84000000 0x87654321 <= Fill test data to dst
=> mw.l 0x84001000 0x12345678 <= Fill test data to src
=> md.l 0x84000000 1; md.l 0x84001000 1 <= Dump src/dst memory contents
84000000: 87654321 !Ce.
84001000: 12345678 xV4.
=> md.l 0x3000000 8 <= Dump PDMA status
03000000: 00000001 11000000 00000003 00000000 ................
03000010: 84000000 00000000 84001000 00000000 ................
=> mw.l 0x3000000 0x3 <= Set channel 0 run and claim bits
=> md.l 0x3000000 8 <= Dump PDMA status
03000000: 40000001 11000000 00000003 00000000 ...@............
03000010: 84000000 00000000 84001000 00000000 ................
=> md.l 0x84000000 1; md.l 0x84001000 1 <= Dump src/dst memory contents
84000000: 87345678 xV4.
84001000: 12345678 xV4.
Signed-off-by: Green Wan <green.wan@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Tested-by: Max Hsu <max.hsu@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20210912130553.179501-4-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/dma/sifive_pdma.c | 16 ++++++++++------
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/hw/dma/sifive_pdma.c b/hw/dma/sifive_pdma.c
index a8ce3e6699..d7d2c53e97 100644
--- a/hw/dma/sifive_pdma.c
+++ b/hw/dma/sifive_pdma.c
@@ -74,7 +74,7 @@ static void sifive_pdma_run(SiFivePDMAState *s, int ch)
uint64_t dst = s->chan[ch].next_dst;
uint64_t src = s->chan[ch].next_src;
uint32_t config = s->chan[ch].next_config;
- int wsize, rsize, size;
+ int wsize, rsize, size, remainder;
uint8_t buf[64];
int n;
@@ -106,11 +106,7 @@ static void sifive_pdma_run(SiFivePDMAState *s, int ch)
size = 6;
}
size = 1 << size;
-
- /* the bytes to transfer should be multiple of transaction size */
- if (bytes % size) {
- goto error;
- }
+ remainder = bytes % size;
/* indicate a DMA transfer is started */
s->chan[ch].state = DMA_CHAN_STATE_STARTED;
@@ -131,6 +127,14 @@ static void sifive_pdma_run(SiFivePDMAState *s, int ch)
s->chan[ch].exec_bytes -= size;
}
+ if (remainder) {
+ cpu_physical_memory_read(s->chan[ch].exec_src, buf, remainder);
+ cpu_physical_memory_write(s->chan[ch].exec_dst, buf, remainder);
+ s->chan[ch].exec_src += remainder;
+ s->chan[ch].exec_dst += remainder;
+ s->chan[ch].exec_bytes -= remainder;
+ }
+
/* indicate a DMA transfer is done */
s->chan[ch].state = DMA_CHAN_STATE_DONE;
s->chan[ch].control &= ~CONTROL_RUN;
--
2.31.1
- [PULL 06/21] hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines, (continued)
- [PULL 06/21] hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines, Alistair Francis, 2021/09/16
- [PULL 07/21] hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines, Alistair Francis, 2021/09/16
- [PULL 08/21] hw/timer: Add SiFive PWM support, Alistair Francis, 2021/09/16
- [PULL 09/21] sifive_u: Connect the SiFive PWM device, Alistair Francis, 2021/09/16
- [PULL 10/21] hw/intc: Rename sifive_clint sources to riscv_aclint sources, Alistair Francis, 2021/09/16
- [PULL 11/21] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT, Alistair Francis, 2021/09/16
- [PULL 12/21] hw/riscv: virt: Re-factor FDT generation, Alistair Francis, 2021/09/16
- [PULL 14/21] hw/dma: sifive_pdma: reset Next* registers when Control.claim is set, Alistair Francis, 2021/09/16
- [PULL 15/21] hw/dma: sifive_pdma: claim bit must be set before DMA transactions, Alistair Francis, 2021/09/16
- [PULL 13/21] hw/riscv: virt: Add optional ACLINT support to virt machine, Alistair Francis, 2021/09/16
- [PULL 16/21] hw/dma: sifive_pdma: allow non-multiple transaction size transactions,
Alistair Francis <=
- [PULL 17/21] hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer, Alistair Francis, 2021/09/16
- [PULL 18/21] docs/system/riscv: sifive_u: Update U-Boot instructions, Alistair Francis, 2021/09/16
- [PULL 19/21] target/riscv: Backup/restore mstatus.SD bit when virtual register swapped, Alistair Francis, 2021/09/16
- [PULL 20/21] target/riscv: csr: Rename HCOUNTEREN_CY and friends, Alistair Francis, 2021/09/16
- [PULL 21/21] hw/riscv: opentitan: Correct the USB Dev address, Alistair Francis, 2021/09/16
- Re: [PULL 00/21] riscv-to-apply queue, Peter Maydell, 2021/09/20