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[PULL 01/21] target/riscv: Update the ePMP CSR address
From: |
Alistair Francis |
Subject: |
[PULL 01/21] target/riscv: Update the ePMP CSR address |
Date: |
Fri, 17 Sep 2021 07:48:44 +1000 |
From: Alistair Francis <alistair.francis@wdc.com>
Update the ePMP CSRs to match the 0.9.3 ePMP spec
https://github.com/riscv/riscv-tee/blob/61455747230a26002d741f64879dd78cc9689323/Smepmp/Smepmp.pdf
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id:
28c908de60b9b04fa20e63d113885c98586053f3.1630543194.git.alistair.francis@wdc.com
---
target/riscv/cpu_bits.h | 4 ++--
target/riscv/cpu.c | 1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 7330ff5a19..ce9dcc030c 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -210,8 +210,8 @@
#define CSR_MTVAL2 0x34b
/* Enhanced Physical Memory Protection (ePMP) */
-#define CSR_MSECCFG 0x390
-#define CSR_MSECCFGH 0x391
+#define CSR_MSECCFG 0x747
+#define CSR_MSECCFGH 0x757
/* Physical Memory Protection */
#define CSR_PMPCFG0 0x3a0
#define CSR_PMPCFG1 0x3a1
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 13575c1408..d4d5961807 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -599,6 +599,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
+ /* ePMP 0.9.3 */
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
--
2.31.1
- [PULL 00/21] riscv-to-apply queue, Alistair Francis, 2021/09/16
- [PULL 01/21] target/riscv: Update the ePMP CSR address,
Alistair Francis <=
- [PULL 02/21] target/riscv: Fix satp write, Alistair Francis, 2021/09/16
- [PULL 03/21] target/riscv: Expose interrupt pending bits as GPIO lines, Alistair Francis, 2021/09/16
- [PULL 04/21] hw/intc: sifive_clint: Use RISC-V CPU GPIO lines, Alistair Francis, 2021/09/16
- [PULL 05/21] hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines, Alistair Francis, 2021/09/16
- [PULL 06/21] hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines, Alistair Francis, 2021/09/16
- [PULL 07/21] hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines, Alistair Francis, 2021/09/16
- [PULL 08/21] hw/timer: Add SiFive PWM support, Alistair Francis, 2021/09/16
- [PULL 09/21] sifive_u: Connect the SiFive PWM device, Alistair Francis, 2021/09/16
- [PULL 10/21] hw/intc: Rename sifive_clint sources to riscv_aclint sources, Alistair Francis, 2021/09/16
- [PULL 11/21] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT, Alistair Francis, 2021/09/16