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[PULL 17/35] target/microblaze: Restrict has_work() handler to sysemu
From: |
Richard Henderson |
Subject: |
[PULL 17/35] target/microblaze: Restrict has_work() handler to sysemu |
Date: |
Thu, 16 Sep 2021 08:30:07 -0700 |
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Restrict has_work() to sysemu.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210912172731.789788-17-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/microblaze/cpu.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 15db277925..36e6e54048 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -92,12 +92,13 @@ static void mb_cpu_synchronize_from_tb(CPUState *cs,
cpu->env.iflags = tb->flags & IFLAGS_TB_MASK;
}
+#ifndef CONFIG_USER_ONLY
+
static bool mb_cpu_has_work(CPUState *cs)
{
return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
}
-#ifndef CONFIG_USER_ONLY
static void mb_cpu_ns_axi_dp(void *opaque, int irq, int level)
{
MicroBlazeCPU *cpu = opaque;
@@ -142,7 +143,7 @@ static void microblaze_cpu_set_irq(void *opaque, int irq,
int level)
cpu_reset_interrupt(cs, type);
}
}
-#endif
+#endif /* !CONFIG_USER_ONLY */
static void mb_cpu_reset(DeviceState *dev)
{
@@ -368,6 +369,7 @@ static const struct TCGCPUOps mb_tcg_ops = {
.tlb_fill = mb_cpu_tlb_fill,
#ifndef CONFIG_USER_ONLY
+ .has_work = mb_cpu_has_work,
.cpu_exec_interrupt = mb_cpu_exec_interrupt,
.do_interrupt = mb_cpu_do_interrupt,
.do_transaction_failed = mb_cpu_transaction_failed,
@@ -386,8 +388,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
device_class_set_parent_reset(dc, mb_cpu_reset, &mcc->parent_reset);
cc->class_by_name = mb_cpu_class_by_name;
- cc->has_work = mb_cpu_has_work;
-
cc->dump_state = mb_cpu_dump_state;
cc->set_pc = mb_cpu_set_pc;
cc->gdb_read_register = mb_cpu_gdb_read_register;
--
2.25.1
- [PULL 09/35] target/alpha: Restrict has_work() handler to sysemu, (continued)
- [PULL 09/35] target/alpha: Restrict has_work() handler to sysemu, Richard Henderson, 2021/09/16
- [PULL 10/35] target/arm: Restrict has_work() handler to sysemu and TCG, Richard Henderson, 2021/09/16
- [PULL 14/35] target/hppa: Restrict has_work() handler to sysemu, Richard Henderson, 2021/09/16
- [PULL 19/35] target/nios2: Restrict has_work() handler to sysemu, Richard Henderson, 2021/09/16
- [PULL 22/35] target/ppc: Restrict has_work() handlers to sysemu and TCG, Richard Henderson, 2021/09/16
- [PULL 29/35] target/tricore: Restrict has_work() handler to sysemu, Richard Henderson, 2021/09/16
- [PULL 16/35] target/m68k: Restrict has_work() handler to sysemu, Richard Henderson, 2021/09/16
- [PULL 23/35] target/riscv: Restrict has_work() handler to sysemu and TCG, Richard Henderson, 2021/09/16
- [PULL 15/35] target/i386: Restrict has_work() handler to sysemu and TCG, Richard Henderson, 2021/09/16
- [PULL 30/35] target/xtensa: Restrict has_work() handler to sysemu, Richard Henderson, 2021/09/16
- [PULL 17/35] target/microblaze: Restrict has_work() handler to sysemu,
Richard Henderson <=
- [PULL 21/35] target/ppc: Introduce PowerPCCPUClass::has_work(), Richard Henderson, 2021/09/16
- [PULL 24/35] target/rx: Restrict has_work() handler to sysemu, Richard Henderson, 2021/09/16
- [PULL 28/35] target/sparc: Restrict has_work() handler to sysemu, Richard Henderson, 2021/09/16
- [PULL 27/35] target/sparc: Remove pointless use of CONFIG_TCG definition, Richard Henderson, 2021/09/16
- [PULL 33/35] tcg/mips: Allow JAL to be out of range in tcg_out_bswap_subr, Richard Henderson, 2021/09/16
- [PULL 35/35] tcg/mips: Drop special alignment for code_gen_buffer, Richard Henderson, 2021/09/16
- [PULL 31/35] accel: Add missing AccelOpsClass::has_work() and drop SysemuCPUOps one, Richard Henderson, 2021/09/16
- [PULL 18/35] target/mips: Restrict has_work() handler to sysemu and TCG, Richard Henderson, 2021/09/16
- [PULL 25/35] target/s390x: Restrict has_work() handler to sysemu and TCG, Richard Henderson, 2021/09/16
- [PULL 32/35] tcg/mips: Drop inline markers, Richard Henderson, 2021/09/16