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[PULL 12/12] escc: fix STATUS_SYNC bit in R_STATUS register
From: |
Mark Cave-Ayland |
Subject: |
[PULL 12/12] escc: fix STATUS_SYNC bit in R_STATUS register |
Date: |
Wed, 8 Sep 2021 12:54:51 +0100 |
After an SDLC "Enter hunt" command has been sent the STATUS_SYNC bit should
remain
high until the flag byte has been detected. Whilst the ESCC device doesn't yet
implement SDLC mode, without this change the active low STATUS_SYNC is
constantly
asserted causing the MacOS OpenTransport extension to hang on startup as it
thinks
it is constantly receiving LocalTalk responses during its initial negotiation
phase.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20210903113223.19551-10-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/char/escc.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/hw/char/escc.c b/hw/char/escc.c
index 9283ed70a6..0fce4f6324 100644
--- a/hw/char/escc.c
+++ b/hw/char/escc.c
@@ -94,6 +94,7 @@
#define W_IVEC 2
#define W_RXCTRL 3
#define RXCTRL_RXEN 0x01
+#define RXCTRL_HUNT 0x10
#define W_TXCTRL1 4
#define TXCTRL1_PAREN 0x01
#define TXCTRL1_PAREV 0x02
@@ -561,7 +562,13 @@ static void escc_mem_write(void *opaque, hwaddr addr,
break;
}
break;
- case W_INTR ... W_RXCTRL:
+ case W_RXCTRL:
+ s->wregs[s->reg] = val;
+ if (val & RXCTRL_HUNT) {
+ s->rregs[R_STATUS] |= STATUS_SYNC;
+ }
+ break;
+ case W_INTR ... W_IVEC:
case W_SYNC1 ... W_TXBUF:
case W_MISC1 ... W_CLOCK:
case W_MISC2 ... W_EXTINT:
--
2.20.1
- [PULL 02/12] tcg: Drop gen_io_end(), (continued)
- [PULL 02/12] tcg: Drop gen_io_end(), Mark Cave-Ayland, 2021/09/08
- [PULL 03/12] sun4m: fix setting CPU id when more than one CPU is present, Mark Cave-Ayland, 2021/09/08
- [PULL 04/12] escc: checkpatch fixes, Mark Cave-Ayland, 2021/09/08
- [PULL 05/12] escc: reset register values to zero in escc_reset(), Mark Cave-Ayland, 2021/09/08
- [PULL 06/12] escc: introduce escc_soft_reset_chn() for software reset, Mark Cave-Ayland, 2021/09/08
- [PULL 07/12] escc: introduce escc_hard_reset_chn() for hardware reset, Mark Cave-Ayland, 2021/09/08
- [PULL 08/12] escc: implement soft reset as described in the datasheet, Mark Cave-Ayland, 2021/09/08
- [PULL 09/12] escc: implement hard reset as described in the datasheet, Mark Cave-Ayland, 2021/09/08
- [PULL 10/12] escc: remove register changes from escc_reset_chn(), Mark Cave-Ayland, 2021/09/08
- [PULL 11/12] escc: re-use escc_reset_chn() for soft reset, Mark Cave-Ayland, 2021/09/08
- [PULL 12/12] escc: fix STATUS_SYNC bit in R_STATUS register,
Mark Cave-Ayland <=
- Re: [PULL 00/12] qemu-sparc queue 20210908, Peter Maydell, 2021/09/10