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Re: [PATCH v10 01/16] target/riscv: Introduce temporary in gen_add_uw()
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From: |
Bin Meng |
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Subject: |
Re: [PATCH v10 01/16] target/riscv: Introduce temporary in gen_add_uw() |
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Date: |
Wed, 8 Sep 2021 13:13:31 +0800 |
On Sun, Sep 5, 2021 at 4:40 AM Philipp Tomsich <philipp.tomsich@vrull.eu> wrote:
>
> Following the recent changes in translate.c, gen_add_uw() causes
> failures on CF3 and SPEC2017 due to the reuse of arg1. Fix these
> regressions by introducing a temporary.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> ---
>
> Changes in v10:
> - new patch
>
> target/riscv/insn_trans/trans_rvb.c.inc | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
- Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic), (continued)
[PATCH v10 15/16] target/riscv: Remove RVB (replaced by Zb[abcs]), Philipp Tomsich, 2021/09/04
[PATCH v10 16/16] disas/riscv: Add Zb[abcs] instructions, Philipp Tomsich, 2021/09/04
[PATCH v10 13/16] target/riscv: Add rev8 instruction, removing grev/grevi, Philipp Tomsich, 2021/09/04
[PATCH v10 01/16] target/riscv: Introduce temporary in gen_add_uw(), Philipp Tomsich, 2021/09/04
[PATCH v10 06/16] target/riscv: Remove the W-form instructions from Zbs, Philipp Tomsich, 2021/09/04
[PATCH v10 07/16] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B), Philipp Tomsich, 2021/09/04
[PATCH v10 14/16] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh, Philipp Tomsich, 2021/09/04