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Re: [PATCH v2 05/22] target/riscv: Allow setting CPU feature from machin
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v2 05/22] target/riscv: Allow setting CPU feature from machine/device emulation |
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Date: |
Mon, 6 Sep 2021 15:33:05 +1000 |
On Thu, Sep 2, 2021 at 9:42 PM Anup Patel <anup.patel@wdc.com> wrote:
>
> The machine or device emulation should be able to force set certain
> CPU features because:
> 1) We can have certain CPU features which are in-general optional
> but implemented by RISC-V CPUs on machine.
> 2) We can have devices which require certain CPU feature. For example,
> AIA IMSIC devices expects AIA CSRs implemented by RISC-V CPUs.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 11 +++--------
> target/riscv/cpu.h | 5 +++++
> 2 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 0ade6ad144..9dc9d04923 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -137,11 +137,6 @@ static void set_vext_version(CPURISCVState *env, int
> vext_ver)
> env->vext_ver = vext_ver;
> }
>
> -static void set_feature(CPURISCVState *env, int feature)
> -{
> - env->features |= (1ULL << feature);
> -}
> -
> static void set_resetvec(CPURISCVState *env, target_ulong resetvec)
> {
> #ifndef CONFIG_USER_ONLY
> @@ -423,18 +418,18 @@ static void riscv_cpu_realize(DeviceState *dev, Error
> **errp)
> }
>
> if (cpu->cfg.mmu) {
> - set_feature(env, RISCV_FEATURE_MMU);
> + riscv_set_feature(env, RISCV_FEATURE_MMU);
> }
>
> if (cpu->cfg.pmp) {
> - set_feature(env, RISCV_FEATURE_PMP);
> + riscv_set_feature(env, RISCV_FEATURE_PMP);
>
> /*
> * Enhanced PMP should only be available
> * on harts with PMP support
> */
> if (cpu->cfg.epmp) {
> - set_feature(env, RISCV_FEATURE_EPMP);
> + riscv_set_feature(env, RISCV_FEATURE_EPMP);
> }
> }
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 59b36f758f..6fe1cc67e5 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -323,6 +323,11 @@ static inline bool riscv_feature(CPURISCVState *env, int
> feature)
> return env->features & (1ULL << feature);
> }
>
> +static inline void riscv_set_feature(CPURISCVState *env, int feature)
> +{
> + env->features |= (1ULL << feature);
> +}
> +
> #include "cpu_user.h"
> #include "cpu_bits.h"
>
> --
> 2.25.1
>
>
- [PATCH v2 03/22] target/riscv: Implement hgeie and hgeip CSRs, (continued)
[PATCH v2 05/22] target/riscv: Allow setting CPU feature from machine/device emulation, Anup Patel, 2021/09/02
[PATCH v2 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs, Anup Patel, 2021/09/02
[PATCH v2 08/22] target/riscv: Allow AIA device emulation to set ireg rmw callback, Anup Patel, 2021/09/02
[PATCH v2 09/22] target/riscv: Implement AIA local interrupt priorities, Anup Patel, 2021/09/02
[PATCH v2 06/22] target/riscv: Add AIA cpu feature, Anup Patel, 2021/09/02
[PATCH v2 07/22] target/riscv: Add defines for AIA CSRs, Anup Patel, 2021/09/02
[PATCH v2 10/22] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32, Anup Patel, 2021/09/02
[PATCH v2 11/22] target/riscv: Implement AIA hvictl and hviprioX CSRs, Anup Patel, 2021/09/02