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Re: [PATCH v1 2/2] target/riscv: Set mtval and stval support
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From: |
Bin Meng |
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Subject: |
Re: [PATCH v1 2/2] target/riscv: Set mtval and stval support |
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Date: |
Sat, 4 Sep 2021 07:58:10 +0800 |
On Sat, Sep 4, 2021 at 1:06 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 9/3/21 1:23 AM, Alistair Francis wrote:
> > + DEFINE_PROP_BOOL("mtval_inst", RISCVCPU, cfg.mtval_inst, true),
>
> Dash not underscore for the prop name, I think.
>
But we also have "priv_spec" :)
The name "mtval_inst" sounds like only for M-mode. Maybe omitting 'm',
and just "tval"?
Regards,
Bin