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[PATCH v3 07/15] target/ppc/power8_pmu.c: add PMC14/PMC56 counter freeze
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH v3 07/15] target/ppc/power8_pmu.c: add PMC14/PMC56 counter freeze bits |
Date: |
Fri, 3 Sep 2021 17:31:08 -0300 |
We're missing two counter freeze bits that are used to further control
how the PMCs behaves: MMCR0_FC14 and MMCR0_FC56. These bits can frozen
PMCs separately: MMCR0_FC14 freezes PMCs 1 to 4 and MMCR0_FC56 freezes
PMCs 5 and 6.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
target/ppc/cpu.h | 2 ++
target/ppc/power8_pmu.c | 25 ++++++++++++++++++++++---
2 files changed, 24 insertions(+), 3 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 76b462c3c8..93f4a46827 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -351,6 +351,8 @@ typedef struct ppc_v3_pate_t {
#define MMCR0_PMCC PPC_BITMASK(44, 45) /* PMC Control */
/* MMCR0 userspace r/w mask */
#define MMCR0_UREG_MASK (MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE)
+#define MMCR0_FC14 PPC_BIT(58) /* MMCR0 Freeze Counters 1-4 bit */
+#define MMCR0_FC56 PPC_BIT(59) /* MMCR0 Freeze Counters 5-6 bit */
#define MMCR1_EVT_SIZE 8
/* extract64() does a right shift before extracting */
diff --git a/target/ppc/power8_pmu.c b/target/ppc/power8_pmu.c
index f584480fde..dd58f57f52 100644
--- a/target/ppc/power8_pmu.c
+++ b/target/ppc/power8_pmu.c
@@ -59,6 +59,15 @@ static uint8_t get_PMC_event(CPUPPCState *env, int sprn)
return extract64(env->spr[SPR_POWER_MMCR1], evt_extr, MMCR1_EVT_SIZE);
}
+static bool pmc_is_running(CPUPPCState *env, int sprn)
+{
+ if (sprn < SPR_POWER_PMC5) {
+ return !(env->spr[SPR_POWER_MMCR0] & MMCR0_FC14);
+ }
+
+ return !(env->spr[SPR_POWER_MMCR0] & MMCR0_FC56);
+}
+
static void update_programmable_PMC_reg(CPUPPCState *env, int sprn,
uint64_t time_delta)
{
@@ -91,13 +100,19 @@ static void update_cycles_PMCs(CPUPPCState *env)
{
uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
uint64_t time_delta = now - env->pmu_base_time;
+ bool PMC14_running = !(env->spr[SPR_POWER_MMCR0] & MMCR0_FC14);
+ bool PMC6_running = !(env->spr[SPR_POWER_MMCR0] & MMCR0_FC56);
int sprn;
- for (sprn = SPR_POWER_PMC1; sprn < SPR_POWER_PMC5; sprn++) {
- update_programmable_PMC_reg(env, sprn, time_delta);
+ if (PMC14_running) {
+ for (sprn = SPR_POWER_PMC1; sprn < SPR_POWER_PMC5; sprn++) {
+ update_programmable_PMC_reg(env, sprn, time_delta);
+ }
}
- update_PMC_PM_CYC(env, SPR_POWER_PMC6, time_delta);
+ if (PMC6_running) {
+ update_PMC_PM_CYC(env, SPR_POWER_PMC6, time_delta);
+ }
}
void helper_store_mmcr0(CPUPPCState *env, target_ulong value)
@@ -138,6 +153,10 @@ static bool pmc_counting_insns(CPUPPCState *env, int sprn,
{
bool ret = false;
+ if (!pmc_is_running(env, sprn)) {
+ return false;
+ }
+
if (sprn == SPR_POWER_PMC5) {
return true;
}
--
2.31.1
- Re: [PATCH v3 03/15] target/ppc: PMU basic cycle count for pseries TCG, (continued)
[PATCH v3 04/15] target/ppc/power8_pmu.c: enable PMC1-PMC4 events, Daniel Henrique Barboza, 2021/09/03
[PATCH v3 05/15] target/ppc: PMU: add instruction counting, Daniel Henrique Barboza, 2021/09/03
[PATCH v3 07/15] target/ppc/power8_pmu.c: add PMC14/PMC56 counter freeze bits,
Daniel Henrique Barboza <=
[PATCH v3 09/15] target/ppc: PMU Event-Based exception support, Daniel Henrique Barboza, 2021/09/03
[PATCH v3 08/15] PPC64/TCG: Implement 'rfebb' instruction, Daniel Henrique Barboza, 2021/09/03
[PATCH v3 10/15] target/ppc/excp_helper.c: EBB handling adjustments, Daniel Henrique Barboza, 2021/09/03
[PATCH v3 06/15] target/ppc/power8_pmu.c: add PM_RUN_INST_CMPL (0xFA) event, Daniel Henrique Barboza, 2021/09/03
[PATCH v3 11/15] target/ppc/power8_pmu.c: enable PMC1 counter negative overflow, Daniel Henrique Barboza, 2021/09/03
[PATCH v3 12/15] target/ppc/power8_pmu.c: cycles overflow with all PMCs, Daniel Henrique Barboza, 2021/09/03
[PATCH v3 13/15] target/ppc: PMU: insns counter negative overflow support, Daniel Henrique Barboza, 2021/09/03
[PATCH v3 14/15] target/ppc/translate: PMU: handle setting of PMCs while running, Daniel Henrique Barboza, 2021/09/03