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[PATCH v2 4/5] hw/char: cadence_uart: Convert to memop_with_attrs() ops
From: |
Bin Meng |
Subject: |
[PATCH v2 4/5] hw/char: cadence_uart: Convert to memop_with_attrs() ops |
Date: |
Wed, 1 Sep 2021 11:27:23 +0800 |
This converts uart_read() and uart_write() to memop_with_attrs() ops.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---
Changes in v2:
- new patch: hw/char: cadence_uart: Convert to memop_with_attrs() ops
hw/char/cadence_uart.c | 26 +++++++++++++++-----------
1 file changed, 15 insertions(+), 11 deletions(-)
diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
index fff8be3619..8bcf2b718a 100644
--- a/hw/char/cadence_uart.c
+++ b/hw/char/cadence_uart.c
@@ -411,15 +411,15 @@ static void uart_read_rx_fifo(CadenceUARTState *s,
uint32_t *c)
uart_update_status(s);
}
-static void uart_write(void *opaque, hwaddr offset,
- uint64_t value, unsigned size)
+static MemTxResult uart_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size, MemTxAttrs attrs)
{
CadenceUARTState *s = opaque;
DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value);
offset >>= 2;
if (offset >= CADENCE_UART_R_MAX) {
- return;
+ return MEMTX_DECODE_ERROR;
}
switch (offset) {
case R_IER: /* ier (wts imr) */
@@ -466,30 +466,34 @@ static void uart_write(void *opaque, hwaddr offset,
break;
}
uart_update_status(s);
+
+ return MEMTX_OK;
}
-static uint64_t uart_read(void *opaque, hwaddr offset,
- unsigned size)
+static MemTxResult uart_read(void *opaque, hwaddr offset,
+ uint64_t *value, unsigned size, MemTxAttrs attrs)
{
CadenceUARTState *s = opaque;
uint32_t c = 0;
offset >>= 2;
if (offset >= CADENCE_UART_R_MAX) {
- c = 0;
- } else if (offset == R_TX_RX) {
+ return MEMTX_DECODE_ERROR;
+ }
+ if (offset == R_TX_RX) {
uart_read_rx_fifo(s, &c);
} else {
- c = s->r[offset];
+ c = s->r[offset];
}
DB_PRINT(" offset:%x data:%08x\n", (unsigned)(offset << 2), (unsigned)c);
- return c;
+ *value = c;
+ return MEMTX_OK;
}
static const MemoryRegionOps uart_ops = {
- .read = uart_read,
- .write = uart_write,
+ .read_with_attrs = uart_read,
+ .write_with_attrs = uart_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
--
2.25.1
- [PATCH v2 0/5] hw/arm: xilinx_zynq: Fix upstream U-Boot boot failure, Bin Meng, 2021/08/31
- [PATCH v2 1/5] hw/misc: zynq_slcr: Correctly compute output clocks in the reset exit phase, Bin Meng, 2021/08/31
- [PATCH v2 4/5] hw/char: cadence_uart: Convert to memop_with_attrs() ops,
Bin Meng <=
- [PATCH v2 3/5] hw/char: cadence_uart: Move clock/reset check to uart_can_receive(), Bin Meng, 2021/08/31
- [PATCH v2 5/5] hw/char: cadence_uart: Ignore access when unclocked or in reset for uart_{read, write}(), Bin Meng, 2021/08/31
- [PATCH v2 2/5] hw/char: cadence_uart: Disable transmit when input clock is disabled, Bin Meng, 2021/08/31